At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

High Speed Serdes IP Electrical Engineer (New College Grad 2024)

This is a unique opportunity to join the 112G/224G SerDes IP R&D Group at Cadence Design Systems. We are looking for a motivated recent EE/CE graduate who will be a key contributor in the areas of: (1) Post-silicon validation, (2) Digital Design, or (3) Firmware Development.

General Requirements:

·        New college grad (2024) with MSEE or MSCE (or similar degree).

·        Energized by learning engineering concepts and methods.

·        Driven to understand and root cause problems comprehensively.

·        Location: San Jose, CA, USA.

Specific Job descriptions and requirements for each position listed below:

(1) Post-Silicon validation

Job Responsibilities: Motivated individuals will participate in all post-Silicon validation

activities working with a small-focused team to test high speed Serdes. You will be able work with high end oscilloscopes, BERTs and other lab equipment and will be working on silicon bring-up and debug, physical layer validation and system level testing. 

Position Requirements: Basic knowledge in analog and digital design. Fluent in scripting and knowledge in python and perl is a plus. Driven to understand and root cause problems comprehensively.

(2) Digital Design

Job Responsibilities: Motivated individuals will participate in all FE digital design activities working with a small-focused team to develop high speed Serdes. You will be able work with the latest Cadence CAD tools and targeting advanced technology nodes from different foundries. 

Position Requirements: Fluent in RTL design. Familiar with design support (verification, cdc checks, linting), Static Timing (constraints and timing analysis), FPGA familiarity is a plus.

DSP and Filter design experience is a plus.  DFT experience is a plus.

(3) Firmware Development

Job Responsibilities: Writing, debugging, and testing the firmware embedded in high-speed transceivers and their adjacent infrastructure as part of a small team.

Position Requirements: Strong coding skills in C and common scripting languages (Python/Perl/TCL etc) are a must. Adjacent skills in signal processing, digital design, optimization, or VLSI technology would be bonuses.

All (3) areas are unique position opportunities to join the 112G/224G SerDes IP R&D Group at Cadence Design Systems. We are looking for a motivated recent EE/CE graduate who will be a key contributor in the areas of: (1) Post-silicon validation, (2) Digital Design, or (3) Firmware Development.

The annual salary range for California is $92,400 to $171,600. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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