Senior Engineer

At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.

Key Responsibilities
Key Responsibilities and JD:

• Sub-system, partition, or block-level physical implementation for sub-5nm/3nm FinFET nodes.
• Floor-planning & Partitioning: Execute chip-top, subsystem, or macro-level floorplanning, pin placement, and power grid/PDN (Power Delivery Network) planning
• Place & Route (PnR): Drive placement, clock tree synthesis (CTS), and signal routing using advanced EDA tools – preferably Cadence Suite
• Timing & Power Closure (STA): Perform multi-corner multi-mode (MCMM) Static Timing Analysis, fix setup/hold violations, and run ECO (Engineering Change Order) iterations – with Critical debug and design convergence ability
• Power Integrity & Electromigration: Analyze and resolve IR-drop, dynamic/static power, and EM (Electromigration) issues using tools like Voltus
• Physical Verification (PV): Run and debug Design Rule Checking (DRC), Layout Versus Schematic (LVS), Antenna checks, and Electrical Rule Checking (ERC)
• Cross-Functional Collaboration: Work directly with RTL designers, DFT (Design for Test) teams, timing/constraint teams, and foundry/EDA application engineers
• Automation: Write and maintain custom design/flow-automation scripts in Tcl, Python, Perl, or Shell

We are known for our extraordinary people who make the impossible possible every day. Questians are driven by hunger, humility, and aspiration. We believe that our company culture is the key to our ability to make a true difference in every industry we reach. Our teams regularly invest time and dedicated effort into internal culture work, ensuring that all voices are heard.

We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace.

Requirements & Qualifications

• Education: Bachelor’s or Master’s degree in Electrical/Electronics Engineering, Computer Engineering, or VLSI/Microelectronics.
• Experience: 3–7 + years  in physical design.
• EDA Tool Proficiency: Cadence tools (Innovus, Genus, Tempus, Voltus, Calibre).
• Advanced Node Knowledge: Direct experience with deep-submicron/FinFET or 7nm/5nm/3nm process rules, multi-Vt optimization, and UPF/CPF low-power design flows.
• Soft Skills: Strong English communication skills for working with global/multinational engineering teams and mentoring junior engineers