Advanced Substrate Design & Process Integration

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At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. 

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.

THE ROLE

Lead the development of next-generation substrate architecture, design rules, and technology platforms that enable AMD's future packaging solutions. This role focuses on substrate design enablement, process integration, design-for-manufacturability (DFM), design-for-yield (DFY), reliability, and electrical performance optimization. This role is for a seasoned engineer to define substrate technology requirements and design methodologies that bridge product needs with manufacturing capabilities. You will work closely with package architects, substrate designers, silicon teams, and manufacturing partners to co-optimize substrate solutions for performance, yield, reliability, and cost.

THE PERSON

The ideal candidate is a technical leader with deep expertise in substrate design architecture, process integration, substrate manufacturing technologies, and package-system co-design. They have developed substrate design rules and technology platforms used in advanced semiconductor products. They understand the tradeoffs between electrical performance, mechanical reliability, manufacturability, and cost, and are skilled at translating product requirements into scalable substrate technologies.

KEY RESPONSIBILITIES

Substrate Architecture & Design Rule Development

• Define substrate technology requirements and design roadmaps for future AMD products.
• Develop substrate design rules, stack-up methodologies, routing architectures, and technology guidelines.
• Establish scalable design infrastructures supporting future substrate technology nodes.
• Drive substrate architecture development across line/space scaling, via technologies, and advanced package integration.

Process Integration

• Lead design-process co-optimization activities across substrate manufacturing technologies.
• Define process-aware design methodologies that improve manufacturability and reduce development risk.
• Collaborate with suppliers to establish process windows, design limitations, and technology capabilities.
• Drive technology readiness assessments for emerging substrate platforms.

Design for Yield (DFY)

• Develop design methodologies that maximize manufacturing yield and process robustness.
• Identify systematic design sensitivities impacting supplier yield and manufacturing cost.
• Define design guidelines and best practices that improve technology scalability.
• Drive design-related yield learning and continuous improvement initiatives.

Reliability Engineering

• Lead substrate reliability strategy and design rule development for mechanical and electrical robustness.
• Develop reliability-aware design guidelines for advanced package applications.
• Partner with reliability teams to understand failure mechanisms and translate learning into improved design requirements.
• Drive technology qualification and design robustness assessments.

Performance Optimization

• Drive substrate architecture solutions for signal integrity, power integrity, and high-speed package performance.
• Collaborate with package and silicon architects to optimize electrical performance across the package system.
• Develop technology solutions supporting future AI, HPC, and heterogeneous integration products.
• Balance performance requirements with manufacturability, reliability, and cost objectives.

Supplier Technology Leadership

• Influence substrate supplier technology roadmaps and capability development.
• Evaluate emerging substrate technologies and manufacturing innovations.
• Establish design requirements and technical targets for development partners.
• Build strategic technology partnerships across the substrate ecosystem.
  
  PREFERRED EXPERIENCE
• Experience in advanced packaging, substrate design, or package technology development.
• Deep expertise in substrate stack-up architecture, routing technologies, HDI design, and advanced package substrates.
• Extensive experience developing substrate design rules for manufacturing and reliability.
• Strong understanding of signal integrity, power integrity, and package electrical performance.
• Experience with design-for-manufacturability, design-for-yield, and design-process co-optimization.
• Strong understanding of substrate manufacturing processes and process integration principles.
• Experience supporting advanced package architectures including chiplet, 2.5D, and heterogeneous integration solutions.
• Proven ability to influence technical direction across multiple organizations and suppliers.
• Demonstrated success presenting strategy and technical roadmaps to senior leadership.

This role is not eligible for visa sponsorship

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.