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Kepler

Ultra-low-voltage computing hardware and memory

Director Physical Design

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeSan Jose, CA, USA$270k - $310k /yrIn-person

About the Job

Requirements

  • A B.E. or M.S. in Electrical Engineering, VLSI, or a related field is required.
  • 15+ years in ASIC/SoC physical design with a proven record of successful silicon tapeouts is required.
  • Expert-level skill with industry-standard physical design tools, flows, and advanced process technologies is required.
  • Deep expertise in clock tree synthesis, timing- and congestion-aware routing, signal-integrity-aware signoff, and low-power/DFT design flows is required.
  • Experience implementing high-performance on-chip interconnect is required.
  • Experience with low-power implementation using UPF-based multi-voltage domains, power gating, retention flops, level shifters, and isolation cells is required.
  • Strong leadership, communication, and project management skills in fast-paced environments are required.
  • A proven record of multiple successful productizations, from physical design through post-silicon qualification and production release, is required.

Responsibilities

  • Lead full-chip physical design from netlist to GDSII signoff for Kepler’s memory products, meeting PPA and schedule goals.
  • Own floorplanning, clock tree synthesis, routing, timing closure, and physical verification; build and improve physical design flows using industry-standard tools.
  • Drive team planning, resource allocation, and milestone, quality, and readiness reviews for successful, on-time tapeouts.
  • Work with architecture, design-for-test, packaging, and manufacturing teams to solve complex integration problems.
  • Develop and review power grid strategies for advanced designs; perform IR drop and electromigration analysis.
  • Partner with the design-for-test team on DFT-aware implementation, including scan, BIST, JTAG/boundary scan, and test-mode power constraints.
  • Own DRC/LVS/ERC signoff and drive clean tapeouts across all design blocks.

Desired Qualifications

  • Physical design experience with high-speed memory interfaces or memory arrays.
  • Experience with 3D innovations or advanced packaging.
  • Strong scripting and automation skills using Tcl, Python, or Perl for flow development, custom analysis, and physical design automation.
  • Prior startup experience delivering high-quality results with lean teams, aggressive timelines, and fast-changing product requirements.

About the Company

Kepler

Ultra-low-voltage computing hardware and memory

Kepler Computing, Inc. develops energy-efficient computing hardware with an ultra-low voltage architecture for memory and logic. Its products include 3D stacked compute and memory units, majority logic gates using input paraelectric capacitors, low-power sequential circuits, and memory bit-cells based on non-linear polar materials. The design uses multi-node, heterogeneous technologies to boost computational power while lowering energy consumption, aiming to outperform traditional silicon-based solutions. Kepler differentiates itself by integrating novel materials (ferroelectric/non-linear polar materials), paraelectric capacitor-based logic, and 3D stacked memory in compact, low-power blocks rather than relying on conventional silicon scaling. Its goal is to deliver more powerful computing hardware that consumes less energy, enabling high-performance computing with significantly improved energy efficiency.

Company size
51-200
Company stage
Grant
Total funding
$734M
Headquarters
Berkeley, CA
Founded
2018

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