V

Velaura

Designs energy-efficient AI silicon and systems

Physical Design Engineer – Staff / Senior Staff / Principal

Full-TimeUpdated
No salary listed
Expert
Bachelor's, Master's
Bengaluru, Karnataka, India
In Person
Hardware EngineeringSilicon & ASIC Design

About the job

Requirements
  • At least 8 years of hands-on experience in physical design implementation and sign-off for complex semiconductor designs.
  • Strong experience delivering high-performance blocks from RTL to GDSII in advanced technology nodes.
  • Proven experience closing high-performance IPs such as CPU, GPU, VPU, memory controller, DDR, NoC, AI accelerators, or other compute-intensive blocks.
  • Strong understanding of synthesis, floorplanning, placement, clock tree synthesis, routing, extraction, timing closure, and physical sign-off.
  • Strong expertise in Static Timing Analysis, timing constraints, clocking methodologies, multi-corner multi-mode closure, and timing ECO implementation.
  • Hands-on experience with physical design and sign-off tools such as Synopsys Fusion Compiler, Cadence Innovus, PrimeTime, StarRC, Calibre, and Apache RedHawk.
  • Experience with advanced process technologies, preferably sub-5nm nodes.
  • Strong understanding of power planning, IR drop, electromigration, signal integrity, congestion analysis, and physical design quality checks.
  • Experience debugging complex design closure issues related to timing, congestion, routing, clocks, power, and physical verification.
  • Strong scripting skills in Tcl, Perl, or Python for flow automation, data analysis, and productivity improvement.
  • Ability to work effectively across multiple projects and with geographically distributed teams.
  • Strong analytical, problem-solving, communication, and technical leadership skills.
Responsibilities
  • Own critical design blocks and drive them from RTL to GDSII through synthesis, floorplanning, place and route, timing closure, and sign-off.
  • Implement and optimize floorplans, power plans, placement, clock tree synthesis, routing, extraction, and sign-off closure for high-performance designs.
  • Drive timing convergence across multiple modes and corners while meeting aggressive frequency, power, area, and schedule goals.
  • Work closely with RTL and architecture teams to understand micro-architecture and evaluate feasibility, timing, power, congestion, and area tradeoffs.
  • Develop and improve physical design methodologies, implementation recipes, and automation flows to optimize PPA and improve design productivity.
  • Perform logic synthesis, placement optimization, CTS, routing, timing ECOs, physical ECOs, extraction, and final sign-off activities.
  • Analyze and resolve complex timing, congestion, clocking, signal integrity, power integrity, and physical verification issues.
  • Perform physical verification and sign-off checks including DRC, LVS, ERC, antenna, density, metal fill, and layout quality checks.
  • Drive EM/IR analysis and collaborate with power integrity teams to ensure robust power delivery and sign-off readiness.
  • Work with industry-standard implementation and sign-off tools such as Synopsys Fusion Compiler, Cadence Innovus, PrimeTime, StarRC, Calibre, and Apache RedHawk.
  • Create and maintain scripts using Tcl, Perl, Python, or other scripting languages to automate physical design tasks and improve flow efficiency.
  • Collaborate with cross-functional teams including RTL, DFT, STA, verification, CAD, packaging, and product engineering to ensure successful silicon delivery.
  • Provide technical leadership in physical design closure, methodology development, and advanced-node implementation challenges.
  • Mentor engineers and help establish best practices for physical design execution, debug, automation, and sign-off quality.
Desired Qualifications
  • Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, VLSI, or a related discipline.
  • Strong understanding of computer architecture, high-performance design concepts, and micro-architecture tradeoffs.
  • Experience working on AI accelerators, high-performance compute, networking, CPU, GPU, or memory subsystem designs.
  • Experience with low-power implementation flows, UPF-based design methodologies, power domains, level shifters, isolation cells, retention strategies, and power-aware sign-off.
  • Good understanding of DFT requirements and their impact on physical implementation, timing, routing, and sign-off.
  • Experience developing or improving physical design methodologies, implementation recipes, and CAD automation flows.
  • Track record of leading complex block-level or subsystem-level physical design execution through tapeout.
  • Ability to mentor junior engineers and provide technical guidance across implementation and sign-off activities.
  • Experience with sub-5nm or leading-edge technology nodes.
  • Experience with high-performance AI, CPU, GPU, VPU, DDR, NoC, or memory controller designs.
  • Experience with hierarchical design implementation and top-level integration.
  • Knowledge of advanced clocking techniques, useful skew, clock mesh, or complex CTS methodologies.
  • Familiarity with package-aware implementation, bump planning, power grid design, and chip-level integration.
  • Experience with timing ECO, functional ECO, metal ECO, and late-stage design closure.
  • Exposure to silicon bring-up, correlation, production support, and post-silicon debug.
  • Experience driving physical design methodology improvements and EDA automation.
  • Strong technical leadership, mentoring, communication, and cross-functional collaboration skills.
  • Background in RTL-to-GDSII physical implementation; high-performance block-level and subsystem-level physical design; synthesis, floorplanning, placement, CTS, routing, and timing closure; Static Timing Analysis and multi-corner multi-mode design closure; advanced-node physical design implementation; physical verification including DRC, LVS, ERC, antenna, density, and metal fill; power integrity, EM/IR analysis, and sign-off; low-power implementation and power-aware design closure; physical design methodology, flow development, and automation; or cross-functional silicon development in advanced semiconductor environments.

About the company

V

Velaura

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Website

Velaura AI designs and manufactures high-density, energy-efficient AI infrastructure, including 3nm ASIC chips, Teraflux mining systems, FluxVision fleet-management software, and AuraLinks rack-level networking. The hardware runs with a systems software stack that optimizes power, cooling, and data throughput, and uses EnergyTune and AutoTune to adjust power draw for grid stability. It differentiates itself with a team of silicon architects from Apple, Google, and Qualcomm, plus a vertically integrated, domestic, hardware-software package focused on reducing energy use in AI infrastructure. Its goal is to enable large-scale AI deployment by delivering powerful, energy-efficient compute and networking that fits sustainable energy grids.

Company Size

51-200

Company Stage

Series A

Total Funding

$424M

Headquarters

Santa Clara, California

Founded

2022

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Benefits

  • Health Insurance
  • Dental Insurance
  • Vision Insurance
  • Flexible Work Hours
  • Professional Development Budget

Growth & Insights and Company News

6 month growth

-35%

1 year growth

-4%

2 year growth

-5%
Velaura AI
Aug 18th, 2026
Velaura AI Raises $110 Million Series A to Advance the Next Generation of Ultra-Low-Power AI Compute Infrastructure - Velaura

Company surpasses $1 billion valuation as investors back proven technology designed to address AI’s mounting power constraints across data centers and Physical AI SANTA CLARA, Calif., August 18, 2026 – Velaura AI, Inc., an AI compute infrastructure company developing ultra-low-power silicon and software technologies, today announced that it has raised $110 million in Series A […]

Finimize
Aug 18th, 2026
Velaura AI hits $1B valuation with $110M Series A for low-power chip designs

Velaura AI has raised $110 million in Series A funding, achieving unicorn status with a valuation exceeding $1 billion. The round was led by Seligman Ventures, with participation from Capricorn Investment Group and existing backers Samsung Catalyst Fund and StepStone Group. The chip designer focuses on low-power designs aimed at reducing energy costs for AI data centres. According to Reuters, the company is positioning efficiency as a key differentiator as the industry faces physical constraints around electricity consumption, cooling requirements, and power delivery capacity. Velaura's approach addresses what investors see as AI's emerging bottleneck: not model sophistication, but the practical limitations of data centre infrastructure.

Startup Scene
Aug 18th, 2026
Saudi-Based Prosperity7 joins $110 million Series A for Velaura AI.

Saudi-Based Prosperity7 joins $110 million Series A for Velaura AI. Aug 20, 2026 Aug 19, 2026 Aug 18, 2026 Aug 20, 2026 The Saudi-backed investor joined Velaura AI's latest round as the US chip startup crossed a $1 billion valuation. Aug 20, 2026 US-based AI infrastructure company Velaura AI has raised $110 million in a Series A round led by Seligman Ventures, with Prosperity7 Ventures joining as a new investor alongside Capricorn Investment Group. The round values Velaura AI at more than $1 billion, as investor interest grows around hardware designed to reduce the energy demands of artificial intelligence workloads. Existing investors including Mayfield, Maverick Silicon, MARA, Premji Invest, Samsung Catalyst Fund and StepStone Group also participated in the round. Velaura AI develops low-power computing technologies for AI infrastructure, including its Titan Core platform, which is designed to improve performance per watt in AI accelerators. The technology is intended for use across data centres as well as robotics, drones and autonomous systems. The company says Titan Core can deliver between two and four times greater performance per watt for mathematical operations used in AI accelerators, and that its technology has already been deployed across more than 30 million ASIC chips. The new capital will be used to accelerate product development and commercialisation, expand engineering and customer-facing teams, and deepen partnerships across the AI infrastructure sector. Velaura's team includes former engineers and executives from companies including Apple, NVIDIA, Google, Qualcomm and Marvell. The company is positioning its technology around the growing cost of powering AI data centres and the expansion of so-called physical AI into robotics and autonomous systems.

HPCwire
Aug 18th, 2026
Velaura AI raises $110M Series A for ultra-low-power AI compute infrastructure.

Velaura AI raises $110M Series A for ultra-low-power AI compute infrastructure. August 18, 2026 Press play to listen to this content SANTA CLARA, Calif., Aug. 18, 2026 - Velaura AI, Inc., an AI compute infrastructure company developing ultra-low-power silicon and software technologies, today announced that it has raised $110 million in Series A financing, bringing its total valuation to more than $1 billion. The round reflects investor conviction in a proven technology foundation, multiple hyperscaler engagements, an experienced leadership team, and a vision for AI compute spanning data centers and Physical AI. Velaura is addressing two of the biggest growth opportunities emerging from the AI megatrend: ultra-low-power compute and Physical AI. Artificial intelligence is increasingly constrained not by the demand for compute, but by the electrical power required to support it. Hyperscalers are investing hundreds of billions of dollars in AI data centers with long lead times on power availability for deployment. Also, as Physical AI with intelligent robots, drones, and autonomous systems move toward mainstream deployment under strict power and thermal limits, energy-efficient computing with purpose-built solutions has become one of the industry's defining challenges. Velaura's Series A financing to address these growth opportunities was led by Seligman Ventures, with participation from new investors Capricorn Investment Group and Prosperity7 Ventures, as well as existing investors including Mayfield, Maverick Silicon, MARA, Premji Invest, Samsung Catalyst Fund, and StepStone Group. The new capital will accelerate the development and commercialization of Velaura's AI compute portfolio, including its recently announced Titan Core silicon platform. It will also support the expansion of the company's engineering and customer-facing teams with deepening collaborations with strategic partners and customers developing next-generation AI infrastructure and Physical AI solutions. The company's leadership team combines decades of experience delivering many of the semiconductor industry's leading high-performance and low-power platforms. Velaura brings together executives and engineers from Apple, NVIDIA, Google, Qualcomm, and Marvell, along with leaders who have built and scaled multiple semiconductor companies and shipped billions of devices. Velaura's Titan Core, proprietary digital chip IP and design platform, delivers a 2-4x improvement in performance per watt for mathematical operations in AI accelerators while maintaining performance. The underlying technology has been validated at commercial scale and deployed in more than 30 million ASICs in leading semiconductor process nodes, demonstrating world-class manufacturing yield and reliability. The company is applying this expertise across AI accelerators while extending the ultra-low-power architecture to Physical AI, including intelligent robots, drones, and other embodied AI systems. "Every advance in AI, from reasoning models to embodied intelligence, creates demand for more compute, and ultimately more power," said Rajiv Khemani, Co-founder and CEO of Velaura AI. "The next era of AI will be defined not only by better models, but also by fundamentally better compute economics. Velaura is building the ultra-low-power silicon and software foundation needed to scale AI from hyperscale data centers to intelligent machines operating in the physical world." About Velaura AI Velaura AI develops ultra-low power silicon and software technologies that enable the next generation of AI infrastructure. Its solutions are designed for hyperscale data centers and Physical AI applications, including robotics, autonomous systems and embodied intelligence. Headquartered in Silicon Valley, Velaura combines proven semiconductor innovation with deep expertise in architecture, silicon design, and software to fundamentally improve the energy efficiency of AI computing. For more information, visit www.velaura.ai. Deep Origin this month announced that its AI drug discovery framework delivered nearly a 31%... AI models are getting better at a rapid pace. They are now able to reason,... The tech industry is fixated on one main metric, the raw number of GPUs accumulated... Jensen Huang believes NVIDIA's chips are becoming much more than expensive pieces of hardware. As... As hybrid cognition deepens, the boundary between biological and artificial embodiment will begin to blur... The Department of Energy today announced a plan to create a new class of open-weight...

PR Newswire
Mar 24th, 2026
Velaura AI unveils Titan Core platform cutting AI accelerator power use by 2x, saving $1,300 per chip

Velaura AI has unveiled Titan Core, a silicon design and intellectual property platform that enables up to 2x lower power consumption for AI accelerators, potentially saving up to 500W on a typical 1,000W GPU. The technology has been validated across over 30 million production ASICs. The platform addresses power constraints in AI data centres by reducing energy required for matrix multiplication operations by 2-4x using proprietary circuit technology at advanced semiconductor nodes. This translates to approximately $1,300 in electricity savings per chip over three years, plus reduced cooling costs. Velaura AI is engaged with several hyperscaler partners for integration at 3nm and 2nm process nodes. The company offers design services and licensable IP that integrate seamlessly into existing chip architectures whilst maintaining full functional equivalence.