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Velaura

Designs energy-efficient AI silicon and systems

RTL Power Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeBengaluru, Karnataka, IndiaIn-person

About the Job

Requirements

  • Strong grasp of the physics and electrical engineering behind average power, peak current, thermal behavior, and voltage droop, and how these concepts relate while remaining independent.
  • Experience designing power management hardware such as digital power meters, throttlers, or thermal and current control loops.
  • Understanding of di/dt, IR drop, and power delivery network behavior, and their impact on timing margin.
  • Experience with clock and reset architecture, including clock gating, PLL management, and reset sequencing.
  • Working knowledge of Verilog or SystemVerilog and modern RTL design methodology.
  • Experience with power estimation and analysis flows from RTL through gate level.
  • Strong debugging and problem-solving skills across hardware and software boundaries.
  • Bachelor of Science or higher in Electrical Engineering, Computer Engineering, or a related field.

Responsibilities

  • Design on-chip power management hardware for the SoC, including digital power meters, activity monitors, and throttlers.
  • Design hardware and software control loops around temperature sensors that hold the die under a defined thermal limit.
  • Design controls that keep the design under defined activity and average power limits as well as instantaneous di/dt limits.
  • Work with architects, physical design, and package teams on voltage droop behavior, power delivery, and adaptive clocking response.
  • Own clock and reset architecture, including clock gating, PLL programming and management, and reset sequencing across power domains.
  • Define and implement power state management, including DVFS, power domains, retention, and low-power flows.
  • Correlate power estimates across RTL, emulation, and silicon, and build telemetry that makes power and thermal behavior visible in the field.
  • Work with firmware and software teams on the interfaces, policies, and telemetry that drive power and thermal management.

Desired Qualifications

  • Experience with DVFS, adaptive voltage scaling, adaptive clocking, or droop detection.
  • Experience with UPF-based low-power design, including power domains, retention, and isolation.
  • Experience correlating pre-silicon power models against silicon measurement.
  • Experience with thermal modeling, sensor placement, or package- and board-level thermal design.
  • Experience with firmware or PMIC interfaces and power management software.
  • Experience with power analysis tools such as PowerArtist, PrimePower, or Joules.
  • Familiarity with robotics, drones, autonomous vehicles, or edge AI systems where power and thermal limits are tight.
  • Experience using AI-assisted design workflows to improve productivity and design exploration.

About the Company

Velaura

Designs energy-efficient AI silicon and systems

Velaura AI designs and manufactures ultra-energy-efficient AI infrastructure, including 3nm ASIC chips, Teraflux mining systems, FluxVision fleet-management software, and AuraLinks rack-level networking. Customers deploy the hardware in data centers, while FluxVision monitors and manages fleets; EnergyTune and AutoTune dynamically adjust power to meet grid stability, and AuraLinks reduces bottlenecks in AI training and inference. The company differentiates itself with a team of silicon architects from Apple, Google, and Qualcomm, plus a patent-pending energy-management approach and a fully integrated hardware-software stack. Its goal is to enable massive AI deployment by delivering powerful, energy-efficient compute and networking that aligns with sustainable energy grids and domestically produced technology.

Company size
51-200
Company stage
Series A
Total funding
$424M
Headquarters
Santa Clara, CA
Founded
2022

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