At Nexperia, innovation starts with deep technical expertise. As a Principal Package Competence Engineer, you will play a key role in advancing semiconductor packaging technologies that enhance the performance, reliability, and competitiveness of our Power MOSFET portfolio. You will act as a subject matter expert, providing technical leadership across package development, assembly technologies, industrialization activities, and strategic technology initiatives.
Working closely with product lines, assembly sites, and R&D teams, you will lead the development of new package solutions, evaluate emerging technologies, and help shape Nexperia's future packaging roadmap.
Why work for us?
Remuneration & Reward – Competitive base salary, Annual Incentive Plan, excellent contributory pension scheme, recognition rewards scheme, income protection, 12 x salary life assurance, visa sponsorship and relocation assistance where applicable.
Health & Wellbeing – Hybrid working policy, 33 days annual leave including bank holidays, flexible benefits scheme, enhanced sick pay, on-site medical centre, subsidised canteen, employee assistance programme, retail and entertainment reductions and a variety of sports and social clubs.
Professional Development – Possibility for funded academic support up to PhD level, employee goal setting and development plans, huge growth potential both internally and globally within the business, opportunity to contribute and work with cutting edge technologies.
Corporate Social Responsibility & Sustainability – A global commitment to becoming carbon neutral by 2035, working with suppliers who embrace and comply with the Nexperia Supplier Code of Conduct, paid time off for every employee to support charitable work.
Diversity, Equity, and Inclusion – Corporate members of Neurodiversity in Business, Disability Confident Employer, dedicated Employee Resource Groups for Women and Neuroinclusion, commitment to increase women in management positions to 30% by 2030.
Talent acquisition based on Nexperia vacancies is not appreciated. Nexperia job adverts are Nexperia copyright © material and the word Nexperia® is a registered trademark.
D&I Statement
As an equal-opportunity employer, Nexperia values diversity not just because it is the right thing to do but because diverse teams perform better. We are dedicated to being inclusive, and a proof point of this dedication is that we were the main partner of the very first Dutch Paralympic Team NL House during the Paris 2024 Paralympic Games. Our recruitment process is inclusive and accessible to all, and we consider all applicants fairly, as well as providing a safe work environment and reasonable adjustments where requested.
In addition, we offer our colleagues the possibility to join employee resource groups such as the Pride Network Group or global and local Women's groups. Nexperia is committed to increasing women in management positions to 30% by 2030.
Nexperia operates as a global supplier of semiconductor components, focusing on discrete semiconductors, logic devices, and MOSFETs. It serves automotive and industrial customers, providing parts that help electronic systems manage power, process signals, and protect data. The company designs, manufactures, and distributes these high-performance components, which are used in applications such as power management, autonomous driving, and data protection. Compared with competitors, Nexperia emphasizes reliability, quality, and targeted expertise in automotive and industrial markets, supported by ongoing improvement and product development. Its goal is to maintain leadership in supplying essential semiconductor parts that enable safer, more efficient, and more capable electronic systems.
Company Size
1,001-5,000
Company Stage
Acquired
Total Funding
$880M
Headquarters
Nijmegen, Netherlands
Founded
1953
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Semiconductor labor shortage throws off efforts to expand capacity. Global chip capacity is expanding rapidly, but workforce shortages could limit how quickly new semiconductor investments translate into supply. Sourceability Team October 16, 2026 min read time The U.S. semiconductor industry's push to grow domestic manufacturing is gaining momentum, but the labor shortage continues to hinder plans. A McKinsey and SEMI Foundation report estimates the U.S. could face a shortage of as many as 157,000 semiconductor workers by 2030. As the U.S. administration considers new tariffs for semiconductor imports, expansion plans by major chipmakers like Samsung, TSMC, Micron, and Intel could struggle to come online. While the U.S. runs into hiccups amidst its reshoring efforts, India continues to grow as an important part of the global semiconductor supply chain. Nexperia and Tata Electronics have announced a broad partnership spanning wafer fabrication, assembly, testing, and technology development. Nexperia plans to produce MOSFETs at Tata's upcoming 300mm fab in Dholera and assemble and test discrete products at its Jagiroad facility. This decision comes amid Nexperia's separation from its parent company late last year due to a Dutch court investigation and ruling. US chip expansion stumbles from labor shortage. The U.S. semiconductor labor shortage is manifesting as a significant bottleneck for the country's chip ambitions. According to a McKinsey and SEMI Foundation report, the U.S. could be short by as many as 157,000 semiconductor workers by the end of the decade. The gap is proving difficult to close, even as chip giants TSMC, Intel, Samsung, and Micron aim to bring new domestic capacity online to support AI demand. Per the report, just 3% of U.S. engineering graduates entering engineering jobs elect a position in the semiconductor industry. Further, nearly three quarters of chip employers report significant difficulty filling engineering roles. For decades, advanced semiconductor manufacturing expertise has been condensed in Asia, which is where the deepest talent pools remain. Contrary to popular belief, chip salaries in the U.S. often fall short of those in Asia, often resting between $127,000 and $187,000. South Korean chip workers have recently seen bonuses alone soar past $500,000 amid strike threats and a culture that puts chip jobs on a pedestal. Stateside, proposed fab timelines leave little runway for the industry to close the labor gap. Samsung aims to start production at its two Taylor, Texas, fabs later this year. The expansion is projected to bring roughly 3,500 chip jobs to the region. TSMC's 3nm fab in Arizona is expected to come online in 2027 after its timeline was moved up from 2028. Thousands of engineers, technicians, equipment specialists, supply chain professionals, and experienced manufacturing personnel are required for each new fab before announced capacity can be counted as reliable output. Unable to meet those demands with U.S. workers, chipmakers including Samsung and SK have been forced to temporarily bring experienced chip talent from South Korea to support fab ramp-ups. Recruiting foreign talent through H-1B visas has become costly and increasingly cumbersome, so chipmakers point to a domestic pipeline as the long-term answer. That pipeline is starting to take shape, largely at the level of academia. TSMC is recruiting from universities to fill roughly 6,000 positions across its first three Arizona fabs. Purdue and Arizona State University have launched semiconductor programs, with Applied Materials contributing $200 million to the latter's cleanroom center. In Ohio, Intel has committed $50 million to scholarship programs. More than 80 community colleges across the U.S. have launched or expanded their semiconductor programs since the CHIPS Act passed in 2022. However, programs like these require years to produce graduates, not considering the additional years of on-the-job learning needed to cultivate expertise, while fabs are trying to open right now. Ultimately, the ongoing struggle to grow a domestic semiconductor workforce is a prime example of why capacity investment alone can't solve constraints on fab expansion. With AI devouring capacity, delays in staffing new facilities could extend existing supply imbalances even as these investments are hailed as a solution to the massive demand for new chips. For now, new U.S. fab announcements should be treated as a long-term supply signal rather than near-term relief. Maintaining diversified sourcing options across regions and manufacturers continues to be a vital strategy in this market for the meantime. Nexperia and Tata expand India's chip ecosystem. According to a Reuters report, Nexperia has announced a partnership with Tata Electronics to manufacture and package chips in India. The agreement covers both front-end wafer fabrication and back-end assembly and testing, as well as technology and ecosystem development. Nexperia now plans to make a broad range of its MOSFET portfolio at the $11 billion 300mm semiconductor fab Tata is building in Dholera. The facility, described as India's first AI-enabled state-of-the-art fab, is designed to handle up to 50,000 wafers per month, with first production runs slated for December 2026. The two will collaborate on assembly and testing of Nexperia's discrete semiconductor products at Tata's packaging facility in Jagiroad. The deal follows a turbulent period for Nexperia after the Dutch government intervened in a September 2025 move the company said was meant to stop operations from shifting to China. Beijing responded by temporarily banning exports of Nexperia chips packaged in Dongguan, leaving global automakers facing a shortage of chips. Both governments have since reversed course, but the company remains geopolitically divided. Notably, Nexperia's current management board has endorsed the Tata agreement, per Reuters. Restrictions on products shipped from the Dongguan packaging site have become a clear example of how high-value assembly lines can be stalled when simple single-source components are disrupted. The Tata agreement gives Nexperia a second geographic option for both wafer production and back-end work, helping address that weakness. It's also a boon for India's chipmaking ambitions. The government's India Semiconductor Mission approved Semicon 2.0 earlier this year, committing roughly $13 billion to furthering its domestic chip industry. As of September 2026, the program has approved 12 projects backed by over $17 billion in combined investment. Tata CEO Randhir Thakur described the deal with Nexperia as a step toward building "a globally competitive, integrated semiconductor manufacturing ecosystem in India." Sourceability Team. The Sourceability Team is a group of writers, engineers, and industry experts with decades of experience within the electronic component industry from design to distribution. Get updates and insights into the electronic component industry that you can't get anywhere else
The next challenge in power electronics. 5 October 2026 At Pretzl Connect 2026, Nexperia argued that GaN versus SiC versus silicon is the wrong question - and that engineers designing for AI data centres, robotics, and electrification need to judge power devices by how they behave in the application, not on paper. For much of the past decade, the case for wide-bandgap (WBG) semiconductors has been made on switching performance. Gallium nitride (GaN) and silicon carbide (SiC) switch faster and waste less energy than silicon, and that efficiency story drove early adoption. According to Nexperia, that chapter is now largely written. "Historically, the perception was that you should focus on the technology that allows you to achieve the best efficiency," said Filippo Scrimizzi, Regional System Application Director at Nexperia. "The world is changing. It is not just performance, it's a mindset - understanding how the market is evolving." Rebuilding capacity. Before turning to WBG, Olaf Vogt, Director and Head of Product, Application Marketing and Engineering, addressed the company's position. Nexperia lost control of its assembly and test sites in Guangdong and Wuxi in October 2025 and has spent the year since rebuilding supply. "This is not an easy time for us, but we have a clear recovery plan, which is already in the implementation phase," said Vogt. Capacity is being significantly expanded at its sites in Malaysia and the Philippines, alongside new foundry and OSAT partnerships. Why the focus is shifting. Scrimizzi pointed to three converging markets: automotive electrification, the energy transition, and AI infrastructure. In data centres, rack power is climbing beyond 250kW, distribution voltages are rising and architectures are moving from single-phase to three-phase. Switching performance gains are well understood; the next gains, Nexperia believes, will come from thermal performance, power density, packaging, system optimisation, and reliability. WBG devices also enable new topologies. In a next-generation bidirectional on-board charger, a bidirectional switch allows the AC/DC and DC/DC stages to merge, removing the DC link capacitor and reducing bill of materials, at the cost of greater control complexity. With cars parked for more than eight hours a day, Scrimizzi said, vehicle-to-grid and vehicle-to-load turn the car into an energy store. The data sheet trap. The session's central argument was that headline specifications mislead. Nexperia compared its 650V Cascode GaN (Gen 1) with a competitor's e-mode GaN device. On paper, the competitor looked equal or better on every parameter: 25 versus 33mΩ RDS(on), 134nC versus 173nC Qoss, and lower thermal resistance. Yet in a 400-to-230V non-isolated buck converter running at 200kHz, the Cascode device achieved higher efficiency at higher power levels. Scrimizzi was careful not to dismiss e-mode: where switching losses dominate, it performs better. But where conduction and soft-switching behaviour matter more, the result reverses. "Before deciding on the final design, don't just trust the number you read in the datasheet," he said. "Test on the bench according to the final application requirements." SiC showed the same pattern. Nexperia's SiC MOSFETs and a competitor's were equivalent at room temperature, but between 25 and 175°C, Nexperia's conduction losses grew by around 1.6 times at 40A, compared with around 2.3 times for the competitor. Matching technology to the application. For AI data centres, Nexperia is lining up 750 and 1200V SiC MOSFETs from 17 to 80mΩ for power supplies, SiC JFETs for hot-swap and solid-state circuit breakers, and very-high-voltage devices above 3.3kV for solid-state transformers. Top-side cooled packages are key to fitting more power into a fixed rack form factor. Humanoid robots are an emerging opportunity for GaN. Each robot uses 25 to 35 body actuators, drawing 0.5 to 2kW per joint, with potentially 200 to 300 GaN switches per robot, according to Yole Group. Most run on 48V batteries, which Nexperia is targeting with its Gen 2 GaN in the 80 to 100V range. Higher switching frequencies mean smaller passives, smoother motor control, and compact drives inside the joint, while silicon still serves low-power joints. Optimisation, not adoption. Nexperia is positioning its integrated device manufacturer model as the way to industrialise WBG at scale. In 2026 its GaN portfolio is set to almost double, with around 60 SiC diodes and MOSFETs releasing, including a 750V SiC MOSFET family in industrial and automotive-qualified versions. Scrimizzi also argued that the package is now as important as the die. "Even the device can be considered a system," he said, pointing to top-side cooled and leadless packages as enablers of thermal performance. His closing message was simple. "We do not believe there is a single technology that will be the winner in the market." The next phase, in other words, is about application optimisation - and bench results, not datasheet tables. Keep up to date with the most important news. ERZIA upgrades environmental ratings of New Space amplifier line. Leicester launches AI student helper. 5 October 2026
Tata-Nexperia India chip route is not supply yet. September 19, 2026 by jimmy India's semiconductor buildout just gained a named customer and a two-site production sketch. That is not the same thing as extra MOSFETs on a distributor shelf. On September 17, Tata Electronics and Nexperia announced a strategic partnership to prepare Nexperia MOSFET production at Tata's upcoming 300 mm fab in Dholera, Gujarat, and to assemble and test Nexperia discrete products at Tata's packaging plant in Jagiroad, Assam. Electronics Weekly reported the deal on September 18. A separate September 18 memorandum with Sumitomo Chemical adds an upstream materials signal around the same Dholera project. The market question is narrower than "will India have another fab?" It is whether an identifiable product portfolio can actually travel a complete, commercially useful route - wafer in, packaged device out - under Nexperia's name. What the Tata-Nexperia partnership actually covers. The joint announcement hosted by Nexperia frames a long-term manufacturing, technology, and ecosystem relationship. MOSFET wafers are the disclosed front-end target at Dholera. Discrete assembly and test are the disclosed back-end target at Jagiroad. What the release does not give is equally important. There is no equity split, no product-level shipment schedule, and no purchase volume. Electronics Weekly's headline uses "jv." The primary text supports calling this a strategic partnership. It does not support asserting that a separately owned joint-venture company has already been formed. The same release puts Tata's combined investment in the two facilities at $14 billion. That is a stated facility investment. It is not the price of the Nexperia agreement, a new payment by Nexperia, or the value of its orders. Treat those dollars as project scale, not as a demand forecast. Why a supplier relationship is not a capacity print. A planned fab is potential capacity. A named manufacturing customer is different evidence: someone intends to use part of that capacity. Linking the two makes the Dholera-Jagiroad story more commercially specific than a generic "addressable market" slide. It still does not justify an immediate utilization number. The disclosed MOSFET scope does not name devices, transfer sequence, wafer allocation, or the customer approvals that would have to travel with a production move. Do not assign Tata's total fab output to Nexperia unless an allocation is disclosed. Do not treat the entire Nexperia discrete catalog as transferable to India on the strength of this announcement. For market analysis, the agreement is a customer-development milestone. It is stronger than a vague statement of demand. It is weaker than a qualified product release and a shipping schedule. Why wafer fab and packaging have to be read together. Diversifying only the front end can leave assembly and test sitting on the same concentrated backend. Diversifying only packaging can leave incoming wafers on the same concentrated fab. A relationship that sketches both stages is commercially more interesting because it creates the option of a more complete additional route. That is an inference about potential, not proof that the route is independent today. Buyers would still need to know where materials originate, which process steps stay shared with existing supply, how test programs are maintained, and how finished devices reach customers. A new geography also does not create a second vendor. Customers may gain another production location inside one supplier's network while keeping the same commercial counterparty and the same product ownership. Location risk can fall without supplier-level exposure disappearing. What the Sumitomo Chemical materials MoU does - and does not - prove. On September 18, Tata Electronics and Sumitomo Chemical signed an MoU to explore supplying semiconductor materials to Dholera and manufacturing some of them in India. The stated scope includes photoresists, functional chemicals, and high-purity process chemicals. Tata describes Dholera as a planned $11 billion, 300 mm fab and cites technology access spanning 28 nm to 110 nm through its PSMC alliance. Those are project-wide statements. They should not be assigned to Nexperia's MOSFET flow unless that mapping is disclosed. The materials MoU matters because an intended device customer and an intended input supplier sit on opposite sides of fab readiness. Neither replaces the other. A MOSFET program needs a repeatable process; that process needs qualified, consistently delivered chemicals. An exploratory memorandum is not an operating local chemical plant, and it is not completed materials qualification. What disclosure would turn this into a sourcing option. Three classes of follow-up would make the supply outlook concrete: * Product scope: named device families, intended applications, and the sequence in which they enter the new route. * Operational evidence: completed process transfer, sample availability, qualification milestones, and confirmed production release. * Commercial evidence: allocated capacity, order commitments, shipment timing, and the share of supply expected to come from the new sites. Those are monitoring items, not conditions the companies have already said they met. Until they appear, the partnership does not establish shorter distributor lead times, lower MOSFET prices, or the end of any existing allocation constraint. Procurement teams can still prepare. Ask for product-specific manufacturing-location data and change-notification plans. There is no basis in the announcement for treating the whole Nexperia portfolio as immediately transferable, interchangeable, or newly available from India. The takeaway. Tata-Nexperia gives India's manufacturing buildout an identifiable prospective product route across both wafer fabrication and packaging. The Sumitomo Chemical materials activity makes the ecosystem story more tangible. The announcements remain different from qualified output. The next useful market signal is a named product moving through that route with a confirmed release and delivery schedule. That is the point at which geographic diversification becomes a sourcing option rather than a strategic intention.
Nexperia and Tata have partnered to manufacture power semiconductors in India. Production will occur at Tata's $11 billion chip plant in Dholera, currently under construction. The companies will also collaborate on chip testing and assembly at Tata's Jagiroad facility. Financial terms were not disclosed. The partnership supports India's semiconductor ambitions, which include incentives for fabrication plants and related investments. The deal comes as Nexperia faces scrutiny over its ties to Chinese parent company Wingtech. A Dutch court has ordered an investigation into Nexperia, whilst separate proceedings examine alleged mismanagement and the relationship with Wingtech.
Nexperia & Aurobay explore GaN and sic powertrain solutions. The companies will evaluate co-design and system-level optimization for traction inverters and power generation systems. September 5, 2026 Nexperia and Aurobay Technologies, part of Horse Powertrain, are considering a strategic partnership to develop advanced power semiconductor technologies for automotive applications. The potential collaboration would bring together Nexperia's capabilities in gallium nitride (GaN) and silicon carbide (SiC) semiconductors with Aurobay Technologies' expertise in powertrain engineering, system design, and integration. The companies are building on earlier work involving Nexperia's GaN devices in Aurobay Technologies' compact power generation system designed for range-extender vehicles. That project highlighted how wide-bandgap (WBG) semiconductor technologies can deliver higher power-conversion efficiency while helping reduce system weight and footprint. It also showed their ability to operate reliably under demanding automotive conditions. Following these results, Nexperia and Aurobay Technologies plan to examine additional opportunities to enhance power electronics architectures for hybrid and electrified vehicles. Potential areas include traction inverters and power generation systems, where semiconductor performance and effective system integration play an important role in determining efficiency, power density, and overall vehicle architecture. The proposed cooperation would place greater emphasis on integrating semiconductor development with powertrain engineering from the early stages of product development. The companies will explore joint engineering and co-design strategies that evaluate semiconductor properties alongside specific powertrain requirements. This system-level approach could help uncover new ways to enhance electrical performance, improve efficiency, and create smaller, more highly integrated powertrain systems. Wide-bandgap (WBG) semiconductors are gaining greater attention in the automotive sector as manufacturers work to improve powertrain efficiency while making electrical systems smaller and lighter. Gallium nitride (GaN) enables fast switching and efficient power conversion, whereas silicon carbide (SiC) is well suited for high-voltage, high-power applications that demand strong thermal performance. Through their collaboration, Nexperia and Aurobay Technologies will examine how both technologies can be integrated into various powertrain designs. The initiative aims to help advance scalable, high-performance propulsion and power-generation systems for upcoming electric and hybrid vehicles. By combining semiconductor innovation with powertrain engineering and integration expertise, the companies hope to identify practical ways to expand the use of WBG power devices across automotive applications.