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GlobalFoundries

Semiconductor foundry delivering specialized chips

Digital Design Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeEgyptIn-person

About the Job

Requirements

  • Bachelor's or master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • At least 1 year of experience in digital RTL design using SystemVerilog or Verilog.
  • Solid understanding of digital design fundamentals, including synchronous design, clock-domain crossing (CDC), finite-state machines (FSMs), pipelining, and low-power techniques.
  • Hands-on experience with industry electronic design automation (EDA) tools for synthesis, lint, CDC, and simulation.
  • Familiarity with scripting in Python, TCL, or Perl for design automation.
  • Experience with high-speed serial interfaces such as SerDes, PCIe, Ethernet, or CXL, or with optical link control.
  • Exposure to silicon photonics, co-packaged optics, or advanced packaging products.
  • Experience with ARM-based system-on-chip (SoC) integration, AMBA protocols (AXI/AHB/APB), and standard IP integration flows.
  • Prior tape-out experience on advanced process nodes.
  • Knowledge of UPF/low-power flows and design-for-test (DFT), including scan, MBIST, and boundary scan.

Responsibilities

  • Develop, document, and maintain RTL using SystemVerilog or Verilog for digital subsystems within the CPO product, including control logic, register interfaces, link management, and DFT structures.
  • Collaborate with architecture, analog/mixed-signal, and photonics teams to define digital interfaces and control schemes for co-packaged optical modules.
  • Own micro-architecture specifications, design reviews, and integration of digital IP into the top-level SoC.
  • Drive synthesis, timing closure, CDC, lint, and low-power (UPF) sign-off in coordination with the physical design team.
  • Perform FPGA prototyping and testing of digital subsystems to validate functionality, accelerate pre-silicon software bring-up, and de-risk RTL ahead of tape-out.
  • Develop and execute UVM-based testing, including building reusable verification components, writing constrained-random tests, and driving functional and code coverage closure.
  • Support verification efforts by collaborating with the design verification team on testbench development, coverage closure, and debug.
  • Participate in tape-out readiness activities, including ECO planning, gate-level simulation, and post-silicon bring-up support.
  • Contribute to design methodology, reuse strategy, and quality improvements across the team.

Desired Qualifications

  • Experience with high-speed serial interfaces such as SerDes, PCIe, Ethernet, or CXL, or with optical link control.
  • Exposure to silicon photonics, co-packaged optics, or advanced packaging products.
  • Experience with ARM-based SoC integration, AMBA protocols (AXI/AHB/APB), and standard IP integration flows.
  • Prior tape-out experience on advanced process nodes.
  • Knowledge of UPF/low-power flows and DFT, including scan, MBIST, and boundary scan.

About the Company

GlobalFoundries

Semiconductor foundry delivering specialized chips

GlobalFoundries is a semiconductor foundry that manufactures chips for a broad range of customers, focusing on feature-rich, reliable technologies for cars, IoT, 5G, and other high-growth markets. It operates by fabricating silicon wafers for customer designs, offering mature, specialized processes rather than chasing the most advanced nodes. This makes it different from peers that prize the latest process nodes; GlobalFoundries emphasizes diversification across a global manufacturing footprint (U.S., Europe, Singapore) and stable supply for essential applications. Its goal is to be a leading supplier of high-volume, specialty manufacturing that enables reliable chips for everyday devices and growing tech markets.

Company size
10,001+
Company stage
IPO
Headquarters
Town of Malta, New York
Founded
2009

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