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Synopsys

EDA software for chip design

Applications Engineering Principal Engineer

Implementation & Technical Account ManagementConfirmed live in the last 24 hours
Full-timeUnited StatesIn-person

About the Job

Requirements

  • A bachelor's degree in Computer Science, Electrical Engineering, or Computer Engineering and 7+ years of hands-on functional verification experience.
  • Deep knowledge of VLSI design flow and verification methodologies, including fluency in SystemVerilog, Verilog, VHDL, or SystemC.
  • Proven experience with front-end verification work, including RTL and testbench coding, simulation debugging, and coverage analysis.
  • Working knowledge of UVM methodology and its deployment in production environments.
  • Proficiency in UNIX/Linux environments and scripting in shell, Perl, or Python to automate workflows and debug customer environments.
  • Strong technical communication skills, including the ability to explain verification concepts to customer engineers and present ROI to directors.
  • Ability to diagnose customer issues, develop action plans, triage tool, configuration, or methodology problems, and follow through on resolution.
  • Ability to balance multiple customer engagements and commitments.

Responsibilities

  • Analyze customer verification environments and methodologies, identify bottlenecks, and recommend deployment strategies for Synopsys Verification Platform tools, including VCS, Verdi, and VIP.
  • Deliver technical demonstrations and proof-of-concept projects showing how Generative AI agents can accelerate chip development workflows.
  • Conduct benchmarking studies comparing customer flows with best practices, then present findings and actionable recommendations to engineering teams and management.
  • Work with R&D and product management to translate customer pain points and feature requests into requirements for next-generation AI-enhanced EDA capabilities.
  • Lead technical discussions and training sessions with customer teams on UVM methodologies, low-power verification techniques, and advanced debugging using Verdi.
  • Build and maintain technical relationships with customers and serve as a trusted advisor for verification problems blocking tapeout.
  • Debug customer testbenches, simulation environments, and scripts to resolve deployment issues and demonstrate tool capabilities in production flows.
  • Accelerate customer adoption of Synopsys Verification Platform, reducing time to tapeout and improving chip quality.
  • Provide customer requirements and use cases to shape the roadmap of AI-enabled verification solutions.
  • Enable customers to shift left in verification, catch bugs earlier, and reduce costly respins.
  • Build reusable deployment methodologies and best practices across customer engagements and industry segments.
  • Expand Synopsys’s footprint within strategic accounts by demonstrating technical value and building trust with engineering teams.
  • Influence adoption of Generative AI in verification and contribute to customer success stories and case studies demonstrating measurable ROI.

Desired Qualifications

  • Experience with low-power design and verification techniques is a strong plus.
  • Hands-on debugging experience using Verdi is a strong plus.

About the Company

Synopsys

EDA software for chip design

Synopsys provides software tools and services for electronic design automation (EDA), helping engineers design, simulate, verify, and optimize semiconductor chips and systems. Its products cover the full design flow, including RTL-to-gating synthesis, place-and-route, timing analysis, verification, and silicon validation, as well as software integrity solutions and hardware-assisted verification. Engineers use these tools to model, simulate, and validate complex chip designs before manufacturing, reducing bugs and improving performance. Compared with many competitors, Synopsys differentiates itself through its broad, end-to-end design toolchain, large ecosystem of IP and integration with simulation and modeling capabilities gained from its 2025 merger with ANSYS, and its global scale and support. The company aims to help designers push the boundaries of chip and system performance, accelerate time-to-market, and enable silicon-to-systems design across a wide range of industries.

Company size
10,001+
Company stage
IPO
Headquarters
Sunnyvale, CA
Founded
1986

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