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Celero Communications

Coherent DSP chips powering AI interconnects

Digital Signal Processing – Forward Error Correction Design Engineer

Electrical EngineeringConfirmed live in the last 24 hours
Full-time$150k - $250k /yrIn-person

About the Job

Requirements

  • A strong theoretical background in coding theory, digital communications, and error correction techniques.
  • Experience developing high-performance forward error correction algorithms for high-speed communication systems.
  • A Master's or Ph.D. degree in Electrical Engineering, Mathematics, Computer Engineering, or a related field is preferred.
  • A strong background in coding theory and error correction algorithms.
  • Experience with FEC schemes for communication systems, particularly soft-decision FEC.
  • Familiarity with LDPC, staircase codes, product codes, or related modern FEC techniques.
  • Experience evaluating coding gain, bit error rate performance, and decoder complexity.
  • Programming experience in C/C++, Python, MATLAB, or similar languages.
  • Experience in modeling communication systems.
  • Familiarity with DSP algorithms for communication systems.
  • Experience with version control systems, specifically GitHub.
  • Familiarity with hardware implementation considerations and languages such as Verilog or VHDL is a plus.

Responsibilities

  • Research, develop, and evaluate forward error correction schemes for high-speed optical communication systems.
  • Design and optimize soft-decision FEC algorithms suitable for high-throughput optical modem implementations.
  • Develop and evaluate coding schemes such as LDPC, staircase codes, or related high-performance FEC architectures.
  • Model and simulate FEC performance in optical communication systems, including interaction with DSP blocks and channel impairments.
  • Analyze performance trade-offs including coding gain, latency, throughput, and implementation complexity.
  • Develop floating-point and fixed-point simulation models for algorithm verification.
  • Implement bit-accurate and cycle-accurate models supporting ASIC implementation.
  • Collaborate closely with DSP, ASIC, firmware, and verification teams to ensure efficient hardware implementation.
  • Document algorithm design and simulation results.

Desired Qualifications

  • Candidates with industry experience are preferred.
  • A team-oriented approach focused on successful delivery of the first product.

About the Company

Celero Communications

Coherent DSP chips powering AI interconnects

Celero Communications designs chips that boost data center connectivity for AI workloads by using coherent DSPs to translate light signals from fiber into electrical data that computers can use. The chips embed algorithms to process optical signals over existing fiber networks, enabling high-bandwidth, long-distance data transfers between AI infrastructure clusters with lower power use. It differentiates itself by focusing on coherent DSP-based optical interconnects for large-scale AI data centers, combining deep analog and digital design expertise from industry veterans and global design centers. Its goal is to make fiber connections faster and more energy-efficient for massive AI deployments, reducing costs as cloud AI accelerators scale up.

Company size
51-200
Company stage
Series C
Total funding
$415M
Headquarters
Irvine, CA
Founded
2024

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