RosaicLabs

Custom x86 chips using Atom RTL

Hardware Engineer - Power

Power Systems EngineeringConfirmed live in the last 24 hours

Full-timeSanta Clara, CA, USA$200k - $275k /yr

About the Job

Requirements

A BS in Electrical Engineering or a related field is required.
At least 8 years designing board-level power electronics, including at least 4 years on server, data center, or high-performance computing platforms.
Shipped power delivery designs for high-performance silicon such as CPU, GPU, ASIC, or AI accelerator, from architecture to production.
Strong fundamentals in DC-DC converter topologies, control loops, power delivery network design, and power integrity.
Hands-on experience with power simulation and analysis tools.
Working knowledge of current server and rack power solutions and major vendor ecosystems for controllers, power stages, and modules.
Laboratory expertise with oscilloscopes, electronic loads, network/frequency-response analyzers, and power analyzers.
Ability to read and guide PCB layout for high-current designs.

Responsibilities

Define board-level power architecture for server motherboards, accelerator modules, and rack power distribution, including 48V/54V busbar to intermediate bus to point of load.
Design high-current, low-voltage power delivery networks for high-performance silicon, including multiphase voltage regulators for core rails exceeding 1,000 A with fast transient response.
Evaluate and select power solutions, including controllers, power stages, power modules, eFuses, hot-swap, and PMICs, and benchmark vendor offerings on efficiency, density, transient performance, cost, and supply risk.
Run power simulations for power delivery network impedance and decoupling, loop stability, transient response, IR drop, efficiency, and thermal derating.
Write schematics and guide PCB layout for power, including stackup, plane design, current density, via sizing, and component placement.
Lead prototype bring-up and validation, including efficiency, ripple, load-step, Bode plots, sequencing, protection, and margining.
Implement and debug digital power telemetry and control using PMBus and AVSBus/SVID with firmware teams.
Partner with silicon vendors to meet their power specifications and coordinate with thermal and mechanical teams on cooling and placement.
Root-cause failures and drive designs through compliance and production.

Desired Qualifications

A master’s degree is preferred.
A PhD is preferred.
Experience with 48V-to-point-of-load architectures, including intermediate bus converters, hybrid/resonant switched-capacitor converters, and vertical or backside power delivery.
Familiarity with OCP standards such as ORv3 and Open Rack power shelves, and with liquid-cooled, high-density racks and accelerator cards.
Knowledge of PSU design, power capping, and rack-level power budgeting.
Experience with safety and regulatory requirements such as UL/IEC 62368-1 and EMI/EMC.

Salary Range: 200000 to 275000 (Currency: USD) (Pay period: per-year-salary)

About Rosaic Labs

Rosaic Labs builds full-platform systems for the agentic AI world: the silicon and software behind what's next. Founded by investor and entrepreneur Amarjit Gill and Peter Bannon, former VP of Engineering at Tesla, we design AI chips and the software that runs on them.

Our team brings together veterans from leading Silicon Valley companies and is growing fast. We are headquartered in Santa Clara, CA, with an office in Austin, TX, and more on the way.

About the role

Rosaic Labs is hiring a Board-Level Power Engineer to own power delivery for our next-generation server platforms. You will design the power architecture that feeds high-performance silicon from the busbar down to the point of load.

This is a hands-on role for an experienced electrical engineer. You will take designs from architecture and simulation through prototype bring-up and validation, working closely with silicon, mechanical, thermal, and system teams and with our power vendors.

Responsibilities

Define board-level power architecture for server motherboards, accelerator modules, and rack power distribution (e.g., 48V/54V busbar to intermediate bus to point of load).

Design high-current, low-voltage power delivery networks for high-performance silicon, including multiphase VRs for core rails exceeding 1,000 A with fast transient response.

Evaluate and select power solutions — controllers, power stages, power modules, eFuses, hot-swap, and PMICs — and benchmark vendor offerings on efficiency, density, transient performance, cost, and supply risk.

Run power simulations: PDN impedance and decoupling, loop stability, transient response, IR drop, efficiency, and thermal derating.

Write schematics and guide PCB layout for power: stackup, plane design, current density, via sizing, and component placement.

Lead prototype bring-up and validation: efficiency, ripple, load-step, Bode plots, sequencing, protection, and margining.

Implement and debug digital power telemetry and control (PMBus, AVSBus/SVID) with firmware teams.

Partner with silicon vendors to meet their power specs, and with thermal and mechanical teams on cooling and placement.

Root-cause failures, and drive designs through compliance and production.

Required qualifications

BS in Electrical Engineering or a related field; MS preferred.

8+ years designing board-level power electronics, with at least 4 years on server, data center, or high-performance computing platforms.

Shipped power delivery designs for high-performance silicon (CPU, GPU, ASIC, or AI accelerator) from architecture to production.

Strong fundamentals in DC-DC converter topologies, control loops, PDN design, and power integrity.

Hands-on experience with power simulation and analysis tools.

Working knowledge of current server and rack power solutions and the major vendor ecosystems for controllers, power stages, and modules.

Lab expertise with oscilloscopes, electronic loads, network/frequency-response analyzers, and power analyzers.

Read and guide PCB layout for high-current designs.

Preferred qualifications

PhD Preferred

Experience with 48V-to-point-of-load architectures, including intermediate bus converters, hybrid/resonant switched-capacitor converters, and vertical or backside power delivery.

Familiarity with OCP standards such as ORv3 and Open Rack power shelves, and with liquid-cooled, high-density racks and accelerator cards.

Knowledge of PSU design, power capping, and rack-level power budgeting.

Experience with safety and regulatory requirements (UL/IEC 62368-1) and EMI/EMC.

About the Company

RosaicLabs

Custom x86 chips using Atom RTL

RosaicLabs designs customized processors by licensing Intel’s Atom technology, including RTL, and integrating an Intel x86 core into its own chip designs. The company, based in Santa Clara, operates in stealth mode and aims to build specialized SoCs for targeted workloads, especially in edge and mobile scenarios where energy efficiency matters. The business model hinges on a strategic agreement with Intel that grants access to core IP and RTL, enabling Rosaic to tailor chips for specific applications rather than using off-the-shelf processors. This arrangement also serves as a potential pathway for Intel to monetize its x86 IP and attract new customers for its foundry services. Rosaic’s goal is to create custom silicon platforms that leverage the established x86 software ecosystem while delivering low-power, efficient computing at the edge.

Company size: 1-10
Company stage: Not listed
Total funding: Not listed
Headquarters: Not listed
Founded: Not listed

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