FuriosaAI

Power-efficient AI inference accelerator chips

Hardware Engineer

Hardware EngineeringConfirmed live in the last 24 hours

Full-timeSeoul, South KoreaNo salary listedIn-person

About the Job

Requirements

A master's or doctoral degree in Electrical Engineering, Computer Engineering, or a related major is required.
Experience with RTL design or verification using Verilog or SystemVerilog, including research or project experience, is required.
Experience using scripting languages such as Python, TCL, or Shell is required.

Responsibilities

Define the core architecture and compute structure of the NPU, validate performance, analyze current large language model compute patterns, develop performance models and cycle-level simulators, analyze area, performance, and accuracy tradeoffs, and design hardware/software integrated execution models with the compiler team.
Design the complete SoC and NoC including the NPU; integrate processing elements, CPUs, and memory controllers; design on-chip networks and AXI interconnects; distribute power and clock domains; establish large-scale SRAM strategies and apply memory compilers; and implement DFT/MBIST, RAS, and fault-handling architecture.
Design high-speed data paths and interfaces connecting chips to external systems, including Die-to-Die, PCIe, proprietary scale-up Ethernet interconnects, and HBM4 memory controller integration and optimization; conduct signal-integrity and power-integrity analysis, design rack-scale architectures, and ensure system reliability.
Develop verification plans from specification documents and verification environments using Python or SystemVerilog/UVM; develop directed and constrained-random tests, run regressions, build hardware-emulation environments and perform emulation-based verification; close coverage, analyze failure root causes, collaborate with design teams to resolve issues, and identify corner cases and potential design errors early.

Desired Qualifications

Experience with chip design, tape-out, or FPGA implementation.
Research experience related to accelerators, processors, or memory hierarchy.
Understanding of AMBA, CDC, UVM, and high-speed interfaces such as PCIe, UCIe, or HBM.
Experience implementing simulators in C++ or performing PPA modeling.
Experience with Chisel or RISC-V.
Recommended expertise for AI chip architecture includes computer architecture, performance modeling and simulator implementation, and deep-learning model structure analysis.
Recommended expertise for SoC design includes RTL design with Verilog/SystemVerilog or Chisel, NoC, and bus protocols.
Recommended expertise for interface design includes high-speed serial interfaces, network and communication protocols, signal processing, error correction, and reliability analysis.
Recommended expertise for design verification includes SystemVerilog/UVM, formal verification, and Python.

About FuriosaAI

FuriosaAI builds high-performance, high-efficiency AI compute for the Inference Era. Founded in 2017 by veteran semiconductor and AI algorithm engineers, Furiosa operates globally with offices in Korea and Silicon Valley, along with a compiler-focused R&D lab in Lisbon.

Our vision is to make AI computing sustainable, enabling access to powerful AI for everyone on Earth. We solve the AI hardware energy and operational cost crisis at the architectural level, rather than through brute force, building the world's first truly AI-native compute platform to unlock the full potential of artificial intelligence for every enterprise.

About the Role

FuriosaAI의 차세대 NPU 개발에 함께할 신입 석·박사 Hardware Engineer를 모집합니다. 전공과 역량에 따라 Architecture, SoC Design, Design Verification, Interface 등 적합한 분야에 배치됩니다.

서류 접수 마감: 2026년 11월 15일(일) 23:59 (KST)

Key Responsibilities

AI Chip Architect - NPU의 핵심 아키텍처와 연산 구조를 정의하고 성능을 검증합니다.
- 최신 LLM 연산 패턴 분석을 통한 NPU Core 설계
- 성능 모델 및 사이클 레벨 시뮬레이터 개발을 통한 면적·성능·정확도 트레이드오프 분석
- 컴파일러 팀과 긴밀히 협업하여 HW/SW 통합 실행 모델 설계
- 권장 기술: 컴퓨터 아키텍처, 성능 모델링 및 시뮬레이터 구현, 딥러닝 모델 구조 분석
SoC Design Engineer - NPU를 포함한 Chip전체 SoC, NoC의 설계를 담당합니다.
- PE, CPU, 메모리 컨트롤러 통합 및 온칩 네트워크(NoC), AXI 인터커넥트 설계
- 전력/클록 도메인 분배, 대규모 SRAM 전략 수립 및 메모리 컴파일러 적용
- DFT/MBIST, RAS(신뢰성·가용성·정비성) 및 결함 허용(Fault handling) 아키텍처 구현
- 권장 기술: RTL 설계(Verilog/SystemVerilog, Chisel), NoC 및 버스 프로토콜
Interface Design Engineer - 칩과 외부 시스템을 연결하는 초고속 데이터 통신 경로 및 인터페이스를 설계합니다.
- D2D(Die-to-Die), PCIe 및 자체 Scale-up 이더넷 인터커넥트 개발
- HBM4 Memory Controller 통합 및 최적화
- SI/PI 분석 및 Rack Scale 구조 설계, 시스템 신뢰성(BER/FIT) 확보
- 권장 기술: 고속 시리얼 인터페이스, 네트워크/통신 프로토콜, 신호처리, 오류 정정 및 신뢰성 분석
Design Verification Engineer - 설계의 기능적 무결성을 증명하고 완벽한 커버리지를 달성합니다.
- Spec 문서를 기반으로 검증 계획 수립 및 Python 또는 SystemVerilog/UVM 기반의 검증 환경 개발
- Directed 및 constrained-random test 개발과 regression 수행, hardware emulation 환경 구축 및 emulation 기반 검증
- Coverage closure 및 failure root cause 분석, 설계팀과의 협업을 통한 문제 해결과 corner case 및 잠재적 설계 오류 조기 발견
- 권장 기술: SystemVerilog/UVM, Formal Verification, Python

Minimum Qualifications

전자공학, 컴퓨터공학 또는 관련 전공 석사/박사 학위 소지자
Verilog/SystemVerilog 기반 RTL 설계 또는 검증 경험 (연구·프로젝트 포함)
Python, TCL, Shell 등 스크립트 언어 사용 경험

Preferred Qualifications

칩 설계, Tape-out 또는 FPGA 구현 경험
Accelerator, Processor, Memory hierarchy 관련 연구 경험
AMBA, CDC, UVM, PCIe/UCIe/HBM 등 High-Speed Interface에 대한 이해
C++ 기반 Simulator 구현 또는 PPA modeling 경험
Chisel, RISC-V 경험

Why Join FuriosaAI

The defining bottleneck of the AI era is building the right hardware and software stack to run it at global scale. Furiosa is solving this challenge holistically from the ground up.

With our flagship chip, RNGD, in mass production today and our next-generation platform in development with Broadcom, we are proving that full-stack, tensor-native compute is the future of AI infrastructure. This is a pivotal moment to join our team, right as we accelerate our global expansion.

At Furiosa, you will:

Solve AI’s Most Urgent Challenge. Help build the high-performance, energy-efficient inference hardware and software required to fulfill the promise of advanced AI.

Pioneer Full-Stack Co-Design. Work with teams that are architecting solutions from silicon up through the compiler (featuring innovations like Tensor Contraction Language and Virtual ISA) and serving frameworks.

Ship Real-World Silicon, Software, and Solutions. Turn breakthrough technology into commercial deployment. RNGD is in mass production with TSMC and running live enterprise workloads for global leaders like LG AI Research and Samsung SDS.

Partner With the Industry's Best. Collaborate across an elite global ecosystem that includes TSMC, Broadcom, SK Hynix, and GUC.

Do Your Life’s Best Work. Join a brilliant, low-ego, mission-driven team in a high-trust environment that values autonomy, intellectual curiosity, and shared ambition.

Contact

[email protected]

About the Company

FuriosaAI

Power-efficient AI inference accelerator chips

FuriosaAI develops AI accelerators for data centers. Its flagship RNGD chip is a power-efficient accelerator designed to boost performance per watt for running large language models and other demanding AI workloads. The hardware is configurable with multiple processing elements to fit different workloads, and it is paired with advanced compiler technology and profiling tools to identify bottlenecks and optimize efficiency. This combination of flexible hardware and software optimization differentiates FuriosaAI from competitors, focusing on maximizing performance while keeping energy use low. The company targets data centers and enterprises that need high-performance, energy-efficient AI solutions, and aims to make AI computing more sustainable and scalable by selling its chips and related software tools and pursuing long-term contracts with large-scale customers.

Company size: 201-500
Company stage: Series D
Total funding: $887.5M
Headquarters: Seoul, South Korea
Founded: 2017

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