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Celero Communications

Coherent DSP chips powering AI interconnects

Principal Analog Design Engineer

Silicon & ASIC DesignUpdated on Nov 1
Full-time$150k - $250k /yrIn-person

About the Job

Requirements

  • A master's degree and/or PhD in Electrical Engineering or a related field, with 5+ years of experience.
  • Strong analog design fundamentals and experience designing analog circuit blocks for broadband amplification, clock generation and distribution, and/or fundamental analog blocks.
  • Experience with analog design and verification tools such as Virtuoso, Spectre, ADE, and post-layout extraction tools.
  • Experience with advanced CMOS design and verification flows, including tools to evaluate self-heating, electromigration, and safe operating area.
  • Knowledge of the fundamentals of electromagnetism, lumped models, and high-frequency design.
  • Strong communication and documentation skills.

Responsibilities

  • Architect, design, and deliver high-performance analog and mixed-signal circuits for next-generation transceivers and other critical high-speed functions.
  • Design high-speed analog circuits, such as high-speed broadband amplifiers (VGA, CTLE, DRV, etc.).
  • Develop clock generation and distribution circuits, including VCOs, PLLs, and clock distribution.
  • Design fundamental analog blocks, including bandgap references, LDOs, and temperature sensors.
  • Develop new techniques for next-generation optical transceivers.
  • Design custom passive components from concept through silicon implementation.
  • Supervise analog layouts within advanced process nodes.
  • Perform system verification and create circuit design specifications.
  • Support silicon bring-up and debugging.
  • Communicate with the team and document work.

Desired Qualifications

  • Experience with electromagnetic simulation tools such as EMX, Momentum, HFSS, or similar tools.
  • Good understanding of analog layouts in FinFET and their effect on high-speed designs.

About the Company

Celero Communications

Coherent DSP chips powering AI interconnects

Celero Communications designs chips that boost data center connectivity for AI workloads by using coherent DSPs to translate light signals from fiber into electrical data that computers can use. The chips embed algorithms to process optical signals over existing fiber networks, enabling high-bandwidth, long-distance data transfers between AI infrastructure clusters with lower power use. It differentiates itself by focusing on coherent DSP-based optical interconnects for large-scale AI data centers, combining deep analog and digital design expertise from industry veterans and global design centers. Its goal is to make fiber connections faster and more energy-efficient for massive AI deployments, reducing costs as cloud AI accelerators scale up.

Company size
51-200
Company stage
Series C
Total funding
$415M
Headquarters
Irvine, CA
Founded
2024

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