Formal Verification Lead - CPU Cores

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Formal Verification Lead, CPU Cores

THE ROLE:

As a Formal Verification Lead, you will provide technical leadership for formal verification of complex, high-performance CPU cores. You will work closely with architects, RTL designers, and verification teams to define and execute formal verification strategies, drive convergence and sign-off, and advance formal methodologies for next-generation processor designs.

THE PERSON:

You have a passion for processor architecture, digital design, and verification. You are a hands-on technical leader with strong analytical, debugging, and problem-solving skills. You collaborate effectively across architecture, design, and verification teams, influence technical direction, mentor engineers, and drive challenging problems to closure across geographically distributed teams.

KEY RESPONSIBILITIES:

• Lead formal verification strategy and execution for complex CPU blocks and subsystems.
• Own formal verification from planning and environment development through convergence, coverage closure, and sign-off.
• Develop and review SystemVerilog Assertions (SVA), properties, assumptions, constraints, abstractions, and formal verification environments.
• Partner with architects and RTL designers to understand design intent, identify corner cases and specification gaps, and improve design verifiability.
• Drive formal convergence and debug through effective abstraction, decomposition, constraints, proof strategies, and tool optimization.
• Define and drive verification quality metrics including property completeness, proof convergence, formal coverage, and sign-off criteria.
• Drive innovation in formal methodologies, automation, reusable infrastructure, and adoption across CPU development.
• Provide technical leadership through verification reviews, complex problem solving, and mentoring across teams and sites.

REQUIRED/PREFERRED EXPERIENCE:

• 13+ years of relevant industry experience, with substantial experience in formal verification of complex digital designs.
• Demonstrated technical leadership in verification of CPU, processor, IP, or complex subsystems.
• Strong hands-on expertise in formal property verification, SVA, formal environments, constraints, abstraction, convergence, and coverage closure.
• Experience with formal tools such as Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal, or equivalent.
• Strong understanding of SystemVerilog/Verilog RTL, computer architecture, and CPU microarchitecture.
• Experience with CPU areas such as pipelines, execution units, caches, memory subsystems, coherency, or control logic is preferred.
• Experience developing formal methodologies, automation, or reusable verification infrastructure is highly desirable.
• Strong scripting skills using Python, Perl, Tcl, Shell, or similar languages.
• Demonstrated ability to mentor engineers, influence technical direction, and lead cross-functional technical initiatives.

ACADEMIC CREDENTIALS:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.