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Astera Labs

Designs chips that connect data center systems

Principal Digital Design Engineer - AI Fabric

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeSan Jose, CA, USA$185k - $230kIn-person

About the Job

Requirements

  • A bachelor's degree in electrical engineering or equivalent is required.
  • At least 8 years of hands-on experience developing complex SoC or silicon products in server, storage, and/or networking markets is required.
  • Experience defining architecture and developing micro-architecture is required.
  • Experience with RTL coding, functional simulation, and synthesis is required.
  • Experience with timing closure and gate-level simulation is required.
  • Experience implementing design-for-test features is required.
  • Production experience with advanced CMOS nodes of 7 nm or smaller is required.
  • Deep expertise in at least one high-speed protocol, such as PCIe, Ethernet, InfiniBand, DDR, or similar, is required.
  • Experience integrating and verifying third-party IP is required.
  • Experience owning block-level design from architecture through GDS is required.
  • Proficiency with Cadence and/or Synopsys digital design flows is required.
  • Familiarity with UVM-based verification methodologies is required.
  • Expertise in silicon bring-up, debug, and failure analysis is required.
  • Ability to balance multiple priorities in a dynamic environment is required.
  • Excellent communication and collaboration skills, including comfort working cross-functionally with global teams, are required.
  • Ability to learn independently, work with minimal supervision, and adapt to changing requirements is required.
  • Ability to translate customer and business needs into technical solutions is required.

Responsibilities

  • Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving digital design.
  • Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues.
  • Lead efforts to achieve timing closure and implement design-for-test features for optimal design performance.
  • Work closely with post-silicon teams to facilitate silicon bring-up and debug.
  • Mentor junior engineers to develop their technical skills and expertise.
  • Contribute to the development and improvement of silicon development processes.
  • Drive designs to production and ensure accountability for quality, schedule, and overall design success.

Desired Qualifications

  • Track record of delivering multiple high-performance designs to production in data-center environments.
  • Hands-on collaboration with embedded firmware teams and a deep understanding of firmware development challenges and constraints.
  • Familiarity with standard embedded processor subsystems such as RISC-V and Arm.
  • Proven contributions to design methodology, CAD automation, or design infrastructure to improve productivity or design quality.

About the Company

Astera Labs

Designs chips that connect data center systems

Astera Labs designs chips and hardware modules that move data between processors, memory and accelerators in data centers. Its customers include cloud providers, chip vendors and equipment makers building servers and large computing clusters for AI and other workloads. Retimers restore signal quality, switches connect devices and memory controllers expand the memory available to computing systems, while COSMOS software monitors and manages these links. The company sells its products directly and through distributors, using outside manufacturers to fabricate and assemble its hardware. Astera Labs was founded in 2017 and is headquartered in San Jose, California.

Company size
501-1,000
Company stage
IPO
Headquarters
San Jose, CA
Founded
2017

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