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Lattice Semiconductor

Low-power FPGAs and design software

Integration Design Engineer

Silicon & ASIC DesignUpdated on Nov 12
Full-timeManila, Metro Manila, PhilippinesNo salary listedIn-person

About the Job

Requirements

  • A BS or MS in Electronics, Computer, or Electrical Engineering is required.
  • At least 5 years of proven, in-depth experience in custom and digital design implementation is required.
  • Expertise in Verilog and SystemVerilog is required.
  • Expertise or a solid understanding of custom design flow is required.
  • Expertise or a solid understanding of semiconductor principles and transistor-level analysis is required.
  • Expertise or a solid understanding of industry-standard schematic and layout entry tools, including Cadence Virtuoso, is required.
  • Expertise or a solid understanding of characterization, performance, and power simulations is required.
  • Expertise or a solid understanding of digital design flow is required.
  • Expertise or a solid understanding of RTL coding and verification is required.
  • Expertise or a solid understanding of lint checks, elaboration and compilation, synthesis, equivalence checks, SDC, and STA using industry-standard tools including Xcelium, Genus, Innovus, and Tempus is required.
  • Expertise in coding and scripting with Perl, TCL, Shell, Skill, or Python is required.
  • Successful background and reference checks and satisfactory proof of the right to work in the Philippines are required.

Responsibilities

  • Integrate different IPs to build the full chip, deliver corresponding models, views, and collateral to functional teams, and complete required checks and simulations for sign-off.
  • Collaborate with Architecture, Software, IP Design, and Physical Design teams to generate the full-chip logical floorplan.
  • Generate a full-chip behavioral model by integrating IP models in alignment with the logical floorplan and the requirements of Software and Verification teams.
  • Deliver the full-chip synthesized netlist and full-chip schematics.
  • Design and implement custom and digital density-specific IPs, such as clock networks, and sectors suitable for full-chip integration.
  • Perform elaboration and compilation, synthesis, equivalence, DFT, timing closure through SPICE simulation and/or STA, and power and performance analysis.
  • Work with other functional teams to debug and resolve issues.
  • Perform full-chip tapeout-gating audits, including electromigration and IR drop analysis, Netlist Electrical Rule Checks, Power Distribution Network extraction, Simultaneously Switching Outputs simulations, and ESD checks.

Desired Qualifications

  • Experience in FPGA/CPLD design and integration is a plus.
  • Knowledge of DFT flow and ATPG generation is an advantage.
  • Experience in IP and full-chip functional verification is a plus.
  • Experience in project leadership and the product development cycle, including planning, resourcing, tapeout, and silicon characterization and validation, is a plus.
  • SPICE is preferred for characterization, performance, and power simulations.

About the Company

Lattice Semiconductor

Low-power FPGAs and design software

Lattice Semiconductor focuses on low-power FPGAs and the software tools that go with them. It provides hardware and software solutions to businesses in industrial, automotive, communications, and consumer electronics markets, selling FPGA devices, software licenses, and support services through a B2B model. Its products, such as MachXO, Lattice Avant, and Lattice Nexus, are programmable logic devices paired with a user-friendly toolchain that enables designers to implement and optimize digital circuits with minimal power consumption. The company differentiates itself by emphasizing low power operation, ease of use, and a complete ecosystem (training and support) designed to accelerate product development and time-to-market. Its goal is to help customers bring reliable, energy-efficient electronic systems to market quickly by providing integrated hardware, software, and services.

Company size
1,001-5,000
Company stage
IPO
Headquarters
Hillsboro, OR
Founded
1983

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