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Positron

Memory-first AI inference silicon for LLMs

ASIC Design Verification Engineer

Hardware Validation & TestingConfirmed live in the last 24 hours
Full-timeAustin, TX, USA

About the Job

Requirements

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • 8+ years of experience in ASIC verification.
  • Expertise in SystemVerilog UVM and simulation tools.
  • Strong knowledge of verification planning, testbench development, and coverage-driven verification.
  • Experience with industry-standard EDA tools, including Cadence, Synopsys, and Mentor Graphics.
  • Hands-on experience with debugging tools, waveform analysis, and scripting in Python, Perl, or TCL.
  • Familiarity with AI/ML accelerators, memory subsystems, and high-speed interconnects.
  • Proven track record of successfully verifying complex ASIC designs.
  • Advanced degree in Electrical or Computer Engineering or a related field.
  • Experience with hardware-software co-verification.
  • Knowledge of formal verification techniques.
  • Understanding of post-silicon validation and bring-up methodologies.

Responsibilities

  • Develop and execute verification strategies for AI inference ASICs.
  • Define and implement comprehensive test plans and verification methodologies.
  • Lead the development of verification environments using SystemVerilog UVM.
  • Create and maintain simulation testbenches, directed tests, and constrained-random tests.
  • Collaborate with design and architecture teams to ensure functional coverage and closure.
  • Drive debugging and root cause analysis of design issues in pre-silicon and post-silicon validation.
  • Work with FPGA and emulation teams for early hardware validation.
  • Manage verification schedules, deliverables, and risk mitigation plans.

About the Company

Positron

Memory-first AI inference silicon for LLMs

Positron develops memory-first AI inference silicon and systems to scale large-language-model serving. Its Atlas systems rely on commodity LPDDR5X memory rather than expensive HBM/CoWoS to boost bandwidth and capacity, enabling more efficient LLM deployment at hyperscale. The company’s next-generation Asimov silicon (tape-out planned for late 2026; production in 2027) pairs compute with very large memory per chip (roughly 288 GB to 2,304 GB) and is designed to be combined into Titan configurations (four to eight Asimov chips) for extremely large models and long context windows. Positron has already deployed Atlas systems in the cloud, including 50+ racks at Oracle Cloud Infrastructure and partnerships with Parasail, Jump Trading, and i3d.net. Its goal is to provide scalable, memory-rich AI inference hardware that lowers cost and increases throughput for serving large language models.

Company size
51-200
Company stage
Series C
Total funding
$1.2B
Headquarters
Reno, NV
Founded
2023

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