Staff Applications Engineering
Synopsys
Staff Applications Engineering
Synopsys
EDA software for chip design
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You have spent years deep in the world of static timing analysis, not just running signoff but actually understanding why a design closes or why it does not, and what needs to change to make it work at scale. You know PrimeTime inside out, not just the commands but the architecture, the corner cases, the workarounds that buy you 10 percent capacity, and the constraints that make or break a tapeout.
You are equally comfortable sitting with a customer's design team debugging a crosstalk violation at 3nm and sitting with R&D mapping out what distributed STA needs to look like for cloud-native workflows. You have seen enough production deployments to know the difference between a demo that looks good and a solution that actually closes timing on a multi-die SoC with 500 modes.
You do not just solve problems, you see patterns across them. When three customers hit the same thermal-aware timing issue, you connect the dots and turn it into a roadmap conversation. You write clear technical summaries, you lead beta programs without waiting for perfect documentation, and you push back when a feature is not ready for production. At Synopsys, you will shape the next generation of timing signoff technology and make sure it works where it matters, in the hands of the teams building the hardest chips in the industry.
You will work within the PrimeTime Product Engineering organization, a team that sits at the intersection of R&D, Product Management, Application Engineering, and customer engagements. This team drives technology leadership and production readiness for timing signoff solutions used by leading semiconductor companies worldwide. You will collaborate closely with R&D engineers developing next-generation STA capabilities, field application engineers supporting customer deployments, and product managers defining strategy and roadmap priorities. The team operates globally and works on some of the most technically demanding signoff challenges in the industry, from multi-die systems to cloud-native workflows to AI-assisted design automation.
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.
Synopsys provides software tools and services for electronic design automation (EDA), helping engineers design, simulate, verify, and optimize semiconductor chips and systems. Its products cover the full design flow, including RTL-to-gating synthesis, place-and-route, timing analysis, verification, and silicon validation, as well as software integrity solutions and hardware-assisted verification. Engineers use these tools to model, simulate, and validate complex chip designs before manufacturing, reducing bugs and improving performance. Compared with many competitors, Synopsys differentiates itself through its broad, end-to-end design toolchain, large ecosystem of IP and integration with simulation and modeling capabilities gained from its 2025 merger with ANSYS, and its global scale and support. The company aims to help designers push the boundaries of chip and system performance, accelerate time-to-market, and enable silicon-to-systems design across a wide range of industries.
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