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Ambiq

Ultra-low power MCUs for IoT wearables

Memory Design Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeSingaporeNo salary listedIn-person

About the Job

Requirements

  • A bachelor's, master's, or PhD in Electrical Engineering, Electronics, or a related discipline.
  • Strong understanding of SRAM architecture, compiler design, and custom memory circuit design.
  • Proven experience developing embedded SRAM or Register File IP for advanced 12nm FinFET technologies and below.
  • Hands-on experience with SRAM compiler development and configurable memory generation.
  • Strong expertise in custom memory characterization and production-quality Liberty (.lib) generation.
  • Deep knowledge of bit-cell operation, sense amplifier design, read/write assist techniques, low-voltage SRAM operation, process variation analysis, and timing and power characterization.
  • Experience with Cadence Virtuoso, Spectre, HSPICE or equivalent SPICE simulators, Cadence Liberate MX, and Monte Carlo simulations.
  • Familiarity with memory compiler architecture and IP delivery flows.
  • Experience supporting silicon bring-up, characterization, debug, and production qualification.
  • Strong scripting skills in Python, Tcl, Perl, or equivalent programming languages.
  • Ability to live the Ambiq Shared Values: Innovate, Collaborate, Focus, Learn, and Achieve.

Responsibilities

  • Design ultra-low-power embedded SRAM and Register File IPs for advanced SoC products.
  • Develop and enhance SRAM compiler architectures supporting multiple memory configurations, banking schemes, and redundancy options.
  • Design and optimize memory peripheral circuits, including sense amplifiers, write drivers, decoders, word-line drivers, pre-charge circuits, read/write assist circuits, redundancy, and repair logic.
  • Optimize memory designs for area, performance, leakage power, dynamic power, yield, and manufacturability; correlate simulation and characterization results with silicon measurements and production test data.
  • Analyze low-voltage failure mechanisms, including read disturb, write failure, read/write margins, retention failures, and process variation effects.
  • Drive memory yield improvement through silicon debug, characterization analysis, and design optimization.
  • Develop automation scripts using Python, Tcl, or Perl to improve compiler generation, characterization efficiency, regression, and design productivity.
  • Collaborate with memory architecture, physical design, timing and STA, DFT/BIST, product and test engineering, foundry partners, and EDA vendors.
  • Support memory IP integration into SoC products from architecture through production release.
  • Document methodologies, design guidelines, characterization results, and silicon learnings.

Desired Qualifications

  • Knowledge of memory redundancy, repair algorithms, ECC, and MBIST integration.

About the Company

Ambiq

Ultra-low power MCUs for IoT wearables

Ambiq designs and sells microcontroller units (MCUs) and system-on-chips (SoCs) that minimize power use for battery-powered IoT and wearable devices. Their chips achieve ultra-low power by combining energy-efficient hardware and software, allowing devices to run longer between charges. They differentiate themselves through a dedicated focus on low-power performance and by earning revenue from silicon sales, technology licensing, and partnerships. Their goal is to enable longer-lasting, energy-efficient endpoint devices across gaming, hearables, industrial IoT, smart homes, wearables, and related markets.

Company size
201-500
Company stage
IPO
Headquarters
Austin, TX
Founded
2010

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