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Lattice Semiconductor

Low-power FPGAs and design software

Integration Design Engineer

Silicon & ASIC DesignUpdated on Nov 12
Full-timeManila, Metro Manila, PhilippinesNo salary listedIn-person

About the Job

Requirements

  • A BS or MS in Electronics, Computer Engineering, or Electrical Engineering is required.
  • At least 5 years of in-depth experience in custom and digital design implementation is required.
  • Expertise in Verilog and SystemVerilog is required.
  • A solid understanding of semiconductor principles and transistor-level analysis is required.
  • A solid understanding of RTL coding and verification is required.
  • Experience coding or scripting in Perl, Tcl, Shell, SKILL, or Python is required.

Responsibilities

  • Integrate different IPs to build the full chip, deliver corresponding models, views, and collateral to functional teams, and complete required checks and simulations for sign-off.
  • Collaborate with Architecture, Software, IP Design, and Physical Design teams to generate a full-chip logical floorplan.
  • Generate a full-chip behavioral model by integrating IP models according to the logical floorplan and the requirements of Software and Verification teams, and deliver the full-chip synthesized netlist and schematics.
  • Design and implement custom and digital density-specific IPs, such as clock networks, and sectors suitable for full-chip integration.
  • Perform elaboration and compilation, synthesis, equivalence, DFT, timing closure using SPICE simulation and/or STA, and power and performance analysis.
  • Work with other functional teams to debug and resolve issues.
  • Perform full-chip tapeout-gating audits, including Electromigration and IR drop analysis, Netlist Electrical Rule Checks, Power Distribution Network extraction, Simultaneously Switching Outputs simulations, and ESD checks.

Desired Qualifications

  • Experience in FPGA/CPLD design and integration is a plus.
  • Experience with industry-standard schematic and layout entry tools such as Cadence Virtuoso.
  • Experience with characterization, performance, and power simulations; SPICE is preferred.
  • Experience with industry-standard digital design tools such as Xcelium, Genus, Innovus, and Tempus for lint checks, elaboration and compilation, synthesis, equivalence checks, SDC, and STA.
  • Knowledge of DFT flow and ATPG generation is an advantage.
  • Experience in IP and full-chip functional verification is a plus.

About the Company

Lattice Semiconductor

Low-power FPGAs and design software

Lattice Semiconductor focuses on low-power FPGAs and the software tools that go with them. It provides hardware and software solutions to businesses in industrial, automotive, communications, and consumer electronics markets, selling FPGA devices, software licenses, and support services through a B2B model. Its products, such as MachXO, Lattice Avant, and Lattice Nexus, are programmable logic devices paired with a user-friendly toolchain that enables designers to implement and optimize digital circuits with minimal power consumption. The company differentiates itself by emphasizing low power operation, ease of use, and a complete ecosystem (training and support) designed to accelerate product development and time-to-market. Its goal is to help customers bring reliable, energy-efficient electronic systems to market quickly by providing integrated hardware, software, and services.

Company size
1,001-5,000
Company stage
IPO
Headquarters
Hillsboro, OR
Founded
1983

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