Security Architect
Velaura
Security Architect
Velaura
Designs energy-efficient AI silicon and systems
Salary Range: 200000 to 300000 (Currency: USD) (Pay period: per-year-salary)
Velaura is designing the compute silicon that will power the next generation of robots, autonomous systems, and intelligent machines operating in the physical world. As Security Architect for our Physical AI System-on-Chip (SoC), you will own the end-to-end security architecture of our silicon platforms—defining how our chips protect the AI models, sensor data, and safety-critical functions that Physical AI systems depend on.
This is a foundational, cross-cutting role. You will set the hardware security strategy from the earliest architecture phase through tape-out and production, working across the silicon, firmware, platform software, and product teams. Because Physical AI systems act on the world—moving, sensing, and making autonomous decisions—the security of our SoC is inseparable from its safety. You will help ensure that Velaura silicon can be trusted in the field, at scale, and over its full lifecycle.
Own the SoC security architecture: define the hardware root of trust, secure boot, key management, secure debug, and lifecycle/provisioning strategy across Velaura’s Physical AI silicon roadmap.
Architect protection for AI workloads and sensitive assets on-chip—model confidentiality and integrity, secure AI/NPU execution, memory isolation, trusted execution environments, and cryptographic acceleration.
Lead threat modeling and security risk assessments for the SoC and its subsystems, translating attacker capabilities (physical, side-channel, fault-injection, supply-chain) into concrete hardware and firmware requirements.
Partner with silicon design, firmware, safety, and platform software teams to embed security requirements into the RTL, boot flow, and SDK—and to review implementations against the architecture.
Define the approach to secure updates, attestation, and device identity so that fielded Physical AI systems remain trustworthy throughout their operational lifetime.
Establish security architecture standards, review processes, and design practices; mentor engineers and raise the security bar across the organization.
Guide alignment with relevant security and functional-safety standards and support certification, audit, and customer security-assurance efforts.
10+ years in security engineering or architecture, with significant experience defining hardware/SoC security for shipping silicon or embedded platforms.
Deep expertise in hardware security primitives: root of trust, secure boot, TEEs (e.g., TrustZone or equivalent), key management, secure debug, and hardware/software cryptographic implementations.
Strong command of applied cryptography and of physical and side-channel attack classes (fault injection, power/EM analysis) and their countermeasures.
Hands-on experience with SoC development flows and the interfaces between RTL/silicon design, firmware, and low-level platform software; ability to specify and review security-relevant hardware and firmware.
Proven ability to lead threat modeling and to drive security requirements across multi-disciplinary teams from architecture through production.
Master’s degree in Electrical/Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
Excellent written and verbal communication skills, with a track record of influencing technical direction and mentoring engineers.
Experience securing AI/ML accelerators or NPUs, including protection of on-device models and inference pipelines.
Familiarity with robotics, autonomous systems, automotive, or other safety-critical domains, and with functional-safety standards (e.g., ISO 26262) alongside security standards (e.g., ISO/SAE 21434, Common Criteria, FIPS 140-3, or PSA Certified).
Experience with post-quantum cryptography, confidential computing, or hardware supply-chain security.
Prior experience at an early-stage or high-growth semiconductor or hardware company, building security functions and practices from the ground up.
Ph.D in Electrical/Computer Engineering, Computer Science, or a related field
Velaura is building next-generation compute technology for cloud, edge, and Physical AI. Our solutions will enable robots, autonomous systems, drones, and other intelligent machines to operate efficiently in the physical world.
This is an opportunity to help build foundational technology at a time when the industry is undergoing fundamental change. You will work alongside experienced leaders, architects, engineers, and operators who have delivered industry-defining products across mobile, cloud, semiconductor, and AI platforms. If you enjoy solving difficult problems, working across disciplines, and helping shape the future of Physical AI, we would love to hear from you.
Velaura is an Equal Opportunity Employer that is committed to inclusion and diversity. Qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, disability or protected veteran status. We also take affirmative action to offer employment
opportunities to minorities, women, individuals with disabilities, and protected veterans.
Velaura is committed to working with qualified individuals with physical or mental disabilities. Applicants who would like to contact us regarding the accessibility of our website or who need special assistance or a reasonable accommodation for any part of the application or hiring process may contact us at: [email protected]. This contact
information is for accommodation requests only. Evaluation of requests for reasonable accommodation will be determined on a case-by-case basis.
Velaura AI designs and manufactures ultra-energy-efficient AI infrastructure, including 3nm ASIC chips, Teraflux mining systems, FluxVision fleet-management software, and AuraLinks rack-level networking. Customers deploy the hardware in data centers, while FluxVision monitors and manages fleets; EnergyTune and AutoTune dynamically adjust power to meet grid stability, and AuraLinks reduces bottlenecks in AI training and inference. The company differentiates itself with a team of silicon architects from Apple, Google, and Qualcomm, plus a patent-pending energy-management approach and a fully integrated hardware-software stack. Its goal is to enable massive AI deployment by delivering powerful, energy-efficient compute and networking that aligns with sustainable energy grids and domestically produced technology.
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