S

SiFive

Designs and sells RISC-V semiconductor cores

Functional Safety & RAS Lead

Hardware EngineeringConfirmed live in the last 24 hours
Full-time

About the Job

Requirements

  • Deep knowledge of functional safety and ISO 26262, including FMEDA, fault modeling, diagnostic coverage, safety cases, and fault-injection planning.
  • Experience applying functional safety standards to semiconductor, processor, or SoC development and working directly with automotive customers.
  • Knowledge of processor or SoC architecture and development sufficient to work effectively with architecture, design, and verification teams.
  • Experience with RAS concepts and mechanisms, including fault detection, error reporting, containment, and recovery.
  • Experience running complex, cross-functional technical programs, including scope, dependencies, risks, and resource needs.
  • A Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline, or equivalent experience.
  • At least 10 years of experience in functional safety, RAS, hardware reliability, or related work in semiconductor, processor, SoC, or other complex hardware development.
  • At least 5 years of experience in semiconductor, SoC, processor-IP, or complex hardware development, including significant architecture or technical-leadership responsibility.
  • Deep experience applying ISO 26262 and functional safety methods such as FMEDA, FMEA, fault-tree analysis, diagnostic coverage, and fault injection.
  • Strong understanding of SoC and IP development from requirements and architecture through verification, release, and customer support.
  • Experience with features intended to detect and address hardware random failures, such as error detection and reporting, fault containment, redundancy, lockstep, ECC/parity, memory protection, or recovery.
  • Experience leading complex, cross-functional technical programs across engineering teams.
  • Ability to work across technical teams, customers, and other stakeholders.

Responsibilities

  • Work with customers and internal teams to understand functional safety and RAS needs, from initial requirements and safety goals through development, assessment, release, and customer support.
  • Partner with the technical architect to define capabilities that meet customer requirements.
  • Define program scope, milestones, dependencies, risks, and engineering resource needs based on customer and product requirements.
  • Coordinate work across architecture, design, verification, software, quality, program management, product, and customer-facing teams.
  • Maintain traceability of safety requirements and decisions through implementation, verification, documentation, product changes, and releases.
  • Identify gaps and technical risks, including dependent failures and common-cause concerns, and work with architect and engineering teams to address them.
  • Support customer assessments, internal reviews, external assessors, audits, and certification activities.
  • Partner with product, sales, and applications teams on customer questions, safety documentation, and product integration guidance.

Desired Qualifications

  • Familiarity with IEC 61508 or other relevant functional safety standards.
  • Active participation in the standards community and ability to influence and establish credibility.
  • Experience with RISC-V processor or SoC architecture and automotive semiconductor IP developed to ASIL-B or ASIL-D objectives.
  • Experience with RAS for data center, AI, robotics, or other high-availability compute products.
  • Experience with reliability analysis or testing, including soft-error-rate modeling or radiation testing.
  • Experience working with certification bodies or external assessors.
  • Familiarity with related standards such as ISO/SAE 21434 or cybersecurity engineering.

About the Company

SiFive

Designs and sells RISC-V semiconductor cores

SiFive designs and sells RISC-V based processors and related IP for use in devices and systems. Its chips come as cores and system-on-chip designs built on the open RISC-V instruction set, enabling customers to integrate high-density, energy-efficient compute into products. Unlike competitors that rely on closed architectures, SiFive leverages openness to offer flexible, scalable, and cost-effective solutions that boost compute density. The company aims to grow the RISC-V ecosystem by delivering high-performance hardware that helps customers tackle data-heavy tasks and build smarter devices.

Company size
501-1,000
Company stage
Series G
Total funding
$772.5M
Headquarters
Santa Clara, CA
Founded
2015

Recently Posted Jobs

Explore more opportunities at SiFive

See more jobs