Physical Design Engineer - Synthesis and Implementation

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.

NVIDIA is looking for best-in-class Physical Design Engineers with expertise in Synthesis to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in crafting our groundbreaking and innovating chips, enjoy working in meaningful, growing and professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

• Own RTL-to-gate synthesis and QoR convergence for complex digital blocks and hierarchical partitions.

• Optimize synthesis strategies, constraints, and flows to meet performance, power, and area targets.

• Analyze design bottlenecks and QoR regressions, collaborating with RTL, timing, architecture, and physical design teams to resolve them.

• Support physical implementation from floorplanning and power planning through routing and timing closure.

• Automate design setup, execution, reporting, and issue triage while improving project-wide methodologies and best known methods.

What we need to see:

• BSEE, MSEE, or equivalent experience.

• 2+ years of experience in synthesis and physical implementation on advanced process nodes.

• Strong proficiency with Synopsys Fusion Compiler, Cadence Genus, or comparable synthesis tools.

• Hands-on experience with synthesis constraints, timing analysis, QoR optimization, and the full place-and-route flow.

• Strong analytical and debugging skills across RTL, synthesis, timing, and physical implementation.

• Proficiency in Python, Perl, Tcl, and Make.

• Strong communication and multi-functional collaboration skills.

We welcome you join our team with some of the most hard-working people in the world working together to promote rapid growth. Are you passionate about becoming a part of a best-in-class team supporting the latest in GPU and AI technology? If so, we want to hear from you.

Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are:
116,000 USD – 189,750 USD for Level 2; and 136,000 USD – 218,500 USD for Level 3.Applications for this job will be accepted at least until November 3, 2026.

This posting is for an existing vacancy. 

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.