A bachelor's or master's degree in Electrical Engineering or a related field is required.
Five to ten years of experience in RTL design and microarchitecture is required.
Strong expertise in RTL design using SystemVerilog or Verilog is required.
Experience developing microarchitecture for complex digital systems is required.
Experience with performance optimization and pipelining techniques is required.
Experience with simulation and debugging tools such as Synopsys VCS or Cadence Xcelium is required.
Familiarity with synthesis and timing concepts, such as using Synopsys Design Compiler, is required.
Strong understanding of digital design fundamentals, including finite-state machines, pipelines, caches, and memory interfaces, is required.
Experience working in ASIC or SoC development environments is required.
Responsibilities
Define and develop microarchitecture specifications from high-level architecture requirements.
Design and implement RTL using SystemVerilog or Verilog for complex digital blocks.
Drive performance, power, and area optimizations at the RTL and microarchitecture level.
Collaborate with verification teams to ensure high coverage and design correctness.
Support integration of IPs into SoC-level environments.
Work with physical design teams on timing closure, synthesis constraints, and floorplan-aware design.
Debug and resolve issues during simulation, gate-level simulation, and silicon bring-up.
Participate in design reviews, architecture discussions, and cross-functional planning.
Contribute to design documentation and methodology improvements.
Desired Qualifications
Experience in one or more of the following domains: CPU, GPU, artificial intelligence or machine-learning accelerators, networking, or high-speed data processing.
Knowledge of memory subsystem design, including SRAM, cache hierarchies, and coherency.
Familiarity with low-power design techniques such as clock gating and power domains.
Exposure to formal verification or linting tools.
Experience with gate-level simulation, SDF annotation, and silicon debug.
Scripting skills in Python or TCL for automation.
Understanding of hardware-software interaction, including firmware and drivers.
Bolt Graphics is a semiconductor startup based in Sunnyvale, CA building the fastest and most efficient graphics processors. We pride ourselves on our first principles approach to solving problems. We are energized by our mission to reduce the barrier of entry for content creation and consumption. Our goal is to enable everyone to easily create, simulate and consume immersive experiences as vividly as they can imagine them.
Our Values
Be Fearless:Unmute yourself. Test boundaries and get proven right.
Remain Adaptable:Stay comfortable in a continuously changing world. If you’re wrong, concede and move on.
Educate Your Ego:Selflessly collaborate towards our shared purpose.
About the role:
As anRTL Design / Microarchitecture Engineer, you will define and implement key microarchitectural components of our SoC/IP. You will work closely with architecture, verification, and physical design teams to deliver high-performance, scalable, and power-efficient designs.
What you'll do:
Define and develop microarchitecture specifications from high-level architecture requirements
Design and implement RTL (SystemVerilog/Verilog) for complex digital blocks
Drive performance, power, and area (PPA) optimizations at the RTL and microarchitecture level
Collaborate with verification teams to ensure high coverage and design correctness
Support integration of IPs into SoC-level environments
Work with physical design teams for timing closure, synthesis constraints, and floorplan-aware design
Debug and resolve issues during simulation, GLS, and silicon bring-up
Participate in design reviews, architecture discussions, and cross-functional planning
Contribute to design documentation and methodology improvements
Required Qualifications:
Bachelor’s/Master’s degree in Electrical Engineering or related field
5–10 years of experience in RTL design and microarchitecture
Strong expertise in:
RTL design using SystemVerilog/Verilog
Microarchitecture development for complex digital systems
Performance optimization and pipelining techniques
Experience with simulation and debugging tools such as:
Synopsys VCS / Cadence Xcelium
Familiarity with synthesis and timing concepts (e.g., using Synopsys Design Compiler)
Strong understanding of digital design fundamentals (FSMs, pipelines, caches, memory interfaces)
Experience working in ASIC/SoC development environments
Preferred Qualifications:
Experience in one or more domains:
CPU, GPU, AI/ML accelerators, networking, or high-speed data processing
Knowledge of memory subsystem design (SRAM, cache hierarchies, coherency)
Familiarity with low-power design techniques (clock gating, power domains)
Exposure to formal verification or linting tools
Experience with GLS, SDF annotation, and silicon debug
Scripting skills (Python/TCL) for automation
Understanding of hardware-software interaction (firmware, drivers)
Bolt is committed to building a diverse and inclusive environment in which we recognize and value each other’s differences as well as fostering a culture that promotes its core values: Professionalism, Integrity, and Respect. As an equal opportunity employer, all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, genetic information, national origin, age, disability, or status as a protected veteran.