Full-Time
Principal Engineer-Design
Posted on 11/23/2025
Microchip Technology
10,001+ employees
Provides embedded hardware, software, tools
No salary listed
Chandler, AZ, USA
In Person
Travel up to 25%; primarily on-site in Chandler, AZ.
 Software Engineering (1) |
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- MS+ years of experience or BS+ years of experience in Electrical/Electronic Engineering
- Demonstrated experience in designing and delivering multi-gigabit PHYs, with a preference for T1 or automotive Ethernet applications
- Solid understanding of DSP elements, including DFE, FFE, echo cancellers, PGA, and related components
- Expertise in RTL coding using Verilog and SystemVerilog
- Proficient in chip-level design and integration activities, such as linting, CDC analysis, and power analysis
- Experience with IP and chip-level synthesis at 16 nanometers and below
- Proficient in static timing analysis and achieving timing closure on complex SoCs
- Hands-on experience with the C programming language
- Proficiency in UNIX scripting languages, including Perl, Python, and csh
- Strong debugging skills in both functional and gate-level simulations
- Familiarity with revision control tools such as CVS, Perforce, and DesignSync, including tagging and release methodologies
- Experience working with lab equipment, including oscilloscopes, logic analyzers, and VNAs
- Excellent analytical, problem-solving, and communication skills
- Experience with automotive and industrial Ethernet standards (e.g., 802.3bp, 802.3ch, 802.3cg) is highly desirable
- Travel Time: 0% - 25%
- Physical Attributes: Hearing, Seeing, Talking, Works Alone, Works Around Others
- Physical Requirements: 80% sitting, 10% standing, 10% walking, 100% inside
- Role involves architecture, design, and verification of high-performance multi-gigabit T1 Ethernet PHYs for automotive, industrial, and enterprise networks
- Collaborate with cross-functional teams to deliver robust, low-power, high-speed solutions that meet stringent industry standards
- Work in areas of RTL design, design verification, synthesis, static timing analysis, and test using an industry leading ASIC design flow
- Train and mentor junior engineers to grow the team’s capability
- Be proactive and motivated with a track record of success in cross-functional and cross-site team environments
- Experience with Verification Methodologies such as UVM/VMM
- Knowledge of Programming Languages such as C++ or SystemC
- Experience with Emulation/FPGA Prototyping for pre-silicon validation
- Knowledge and exposure to complete SoC RTL to GDS to silicon release flow is desired
Microchip Technology provides embedded system solutions by selling hardware components like microcontrollers, FPGAs, silicon carbide devices, and analog parts, along with software and development tools. Its products work as configurable silicon paired with software and toolchains that engineers use to design and implement embedded systems in domains such as automotive, industrial, consumer electronics, aerospace, and telecom. The company differentiates itself through a broad product portfolio, a strong education and support ecosystem (including Microchip University), and direct B2B sales and services that help customers develop and deploy solutions. Its goal is to be a leading provider of end-to-end embedded system solutions, generating revenue from hardware, software licenses, development tools, and related services.
Company Size
10,001+
Company Stage
IPO
Headquarters
Chandler, Arizona
Founded
1989
Simplify's Take
What believers are saying
- Q1 CY2026 revenue hit $1.31B, up 35% YoY, with Q2 guidance at $1.46B.
- Inventory days dropped to 184, boosting margins to 16.6% from negative 10.3%.
- Intel MD-990-0011-B modules target expanding 5G vRAN and AI data center markets.
What critics are saying
- NXP SE050-C erodes 15-20% embedded security share within 12-18 months.
- Intel Granite Rapids Xeon 6 obsoletes TS1800 in OCP data centers by Q3 2026.
- EU CRA enforcement in January 2027 delays TrustFLEX adoption due to certification gaps.
What makes Microchip Technology unique
- TA101 TrustFLEX and TrustMANAGER enable PKI-based authentication for IEC 62443 compliance.
- TS1800 Root of Trust supports NIST PQC algorithms like ML-DSA for data centers.
- LAN878x PHYs integrate MACsec security for ISO 26262 ASIL-B automotive systems.
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Benefits
Health Insurance
401(k) Retirement Plan
Stock Options
Performance Bonus
Employee Stock Purchase Plan
Company News
Microchip Technology has partnered with Sunny Smartlead, a global automotive camera module supplier and subsidiary of Sunny Optical Technology Group, to expand the Automotive SerDes Alliance Motion Link (ASA-ML) ecosystem. Sunny Smartlead is introducing Advanced Driver-Assistance Systems camera modules built on Microchip's VS700 family of ASA-ML devices. The collaboration combines Microchip's ASA-ML serialiser technology with Sunny Smartlead's camera expertise to help automotive manufacturers develop standardised ADAS camera solutions for Software-Defined Vehicles. ASA-ML technology features integrated security and timing capabilities, including link-layer authentication and precision time synchronisation across sensors. The partnership aims to create a production-ready, multi-vendor camera ecosystem around ASA-ML, offering an alternative to proprietary technologies. Sunny Smartlead's camera modules integrate Microchip's VS775S serialiser to support development within the ASA-ML ecosystem.
Everspin Technologies expands on-shore MRAM manufacturing capacity. Strategic manufacturing agreement with Microchip Technology to expand production capacity and strengthen long-term supply. Everspin Technologies Inc. announced its strategic manufacturing agreement with Microchip Technology, Inc. to expand production capacity and strengthen long-term supply.The company has entered into an initial 10-year agreement, that can be extended in 2-year increments, with Microchip Technology to augment its onshore manufacturing capacity for MRAM and Tunnel Magnetoresistive (TMR) sensor products. The firm will establish a copy exact (plus) MRAM line to manufacture MRAM and TMR sensor products currently produced at its line in Chandler, AZ. "Everspin is expanding its manufacturing footprint to support the next phase of MRAM adoption, as customers look for both long-term supply stability and higher-density, more capable solutions," says Sanjeev Aggarwal, president and CEO. "Our partnership with Microchip adds the production scale to support demand while continuing to advance our MRAM roadmap." Under the agreement, Everspin will stand up its industry magnetic technology and manufacturing process at a Microchip fabrication facility in Oregon. The company will retain ownership of the intellectual property and manufacturing process while utilizing Microchip's foundry services capacity. This expanded capacity will leverage Everspin's strong balance sheet and partnerships. "Microchip is pleased to collaborate with Everspin and provide foundry services from its large and expandable manufacturing capacity in our Oregon Fab," said Michael Finley, SVP, fab operations, Microchip'. The agreement will provide Everspin and its customers with several strategic benefits: * Increased wafer capacity to support growth plans * On-shore second source for MRAM and TMR sensor products * Continuity of supply lasting well into the next decade * Additional opportunities for Everspin to continue R&D programs advancing MRAM capabilities for next-gen use cases and workloads * International Traffic in Arms Regulations (ITAR) wafer processing capabilities The company will continue to manufacture MRAM and TMR sensor wafers in its Chandler, AZ facility co-located at NXP. The company plans to leverage its 20 years of MRAM production experience from Everspin's Chandler operation as a benchmark for process bring up at Microchip ensuring a timely and seamless process installation. The company expects the first products to ship from the Everspin-Microchip collaboration in the 2nd half of 2027. Read also: 64Mb xSPI STT-MRAM completes production qualification, and 128Mb and 256Mb xSPI STT-MRAM advancing through final qualification phases Read bandwidth of up to 400MB/s and write bandwidth of approximately 90MB/s, over 400 times faster than NOR flash, and write endurance up to 10 times higher than typical NOR AEC-Q100 Grade 1 MRAM delivers 10-year data retention at 125°C, 48-hour burn-in, and unlimited endurance for mission-critical systems Integrating Everspin's MRAM technologies with Quintauris' reference architectures and real-time platforms
Reference platform targets robust 10BASE-T1S Ethernet design. New Products | April 4, 2026 By Jens Nickel A new system-level reference design platform aims to accelerate adoption of Single-Pair Ethernet (SPE) in industrial and building automation applications. Developed through a collaboration between Arrow, Microchip, Bourns and Amphenol, the REF_SPE_T1S platform provides a practical evaluation environment for engineers transitioning from legacy fieldbus technologies to Ethernet at the edge. The platform addresses a key challenge in SPE deployment: ensuring signal integrity and electromagnetic compatibility (EMC) in electrically noisy environments. It also highlights the growing importance of magnetics design in achieving reliable Ethernet communication beyond the PHY layer. Magnetics design drives SPE performance The REF_SPE_T1S platform is built around Microchip's LAN8670 10BASE-T1S PHY and an IEC 63171-6 compliant SPE connector from Amphenol. At its core is an integrated magnetics solution from Bourns, combining an isolation transformer and common-mode choke (CMC) in a single component. The design demonstrates how the magnetic interface between PHY and cable plays a critical role in overall SPE performance. According to the developers, integrated transformer-based isolation significantly improves common-mode noise rejection and galvanic isolation, particularly at low frequencies - an area where capacitor-only isolation approaches can fall short. This enhanced noise suppression helps maintain signal integrity and stable connections in harsh industrial environments, where conducted and radiated interference can degrade communication reliability. The approach also improves emissions margins, supporting compliance with EMC requirements. Supporting the shift from fieldbus to Ethernet As industrial systems migrate away from legacy communication standards such as CAN and RS-485, SPE is emerging as a key enabler for Ethernet connectivity down to sensor and actuator level. The REF_SPE_T1S platform is positioned as a tool to support this transition by providing measurable insights into network robustness. The USB-powered evaluation board allows engineers to compare transformer-based isolation with capacitor-based designs in real time. It supports both point-to-point and multidrop 10BASE-T1S configurations, enabling validation of network stability and channel performance before finalising product designs. Target applications include industrial automation, HVAC and building control systems, as well as embedded edge devices requiring reliable, low-speed Ethernet connectivity. By offering a reference schematic and live testing environment, the platform is intended to reduce design risk and accelerate time-to-market for SPE-enabled products. Overall, the REF_SPE_T1S highlights how careful optimisation of the physical layer - including magnetics and isolation strategy - remains critical as Ethernet continues to expand into increasingly demanding edge environments. At the Arrow webpage developers can apply for samples. Linked Articles
Arrow, Microchip, Bourns, and Amphenol produce reference design for SPE. Arrow, Microchip, Bourns, and Amphenol have come up with an evaluation platform - the 10BASE-T1S REF_SPE_T1S reference design board. The design assists engineers in adopting Single Pair Ethernet (SPE) by addressing the magnetic connection that links data to the physical cable and enables system-level evaluation of signal integrity, EMC behaviour, and noise immunity in real-world applications. SPE performance is defined not only by the PHY but by the quality of the magnetic interface that connects it to the cable. Built around Microchip's LAN8670 10BASE-T1S PHY and IEC 63171-6 compatible Amphenol's SPE connector, this design demonstrates how Bourns integrated isolation transformer and common-mode choke (CMC) magnetics (Model SM91081AL) play a critical role at the physical layer. By significantly improving common-mode noise rejection and galvanic isolation especially at low frequencies, the board helps maintain signal integrity and connection stability in electrically noisy industrial and building-automation environments. As industries transition away from legacy systems like CAN or RS-485, there is an increasing requirement for reliable Ethernet connectivity at the "edge," including sensors and actuators. By utilizing an integrated transformer design instead of traditional capacitor-only isolation approaches, this evaluation board offers improved signal clarity and connectivity, particularly through superior low-frequency noise attenuation and enhanced immunity to conducted and radiated interference. This approach provides a necessary margin for error against the electrical noise common in industrial settings and supports improved EMC and emissions performance, helping design engineers to meet regulatory compliance requirements more efficiently. Whether intended for factory automation, HVAC systems, or building controls, this SPE USB-powered platform provides a live demonstration of network robustness. Engineers can directly compare transformer-based isolation against capacitor isolation, observe common-mode noise suppression behaviour, and evaluate EMC and emissions performance. Arrow provides this tool as a reference schematic solution for new designs which also allows designers to measure network stability in both point-to-point and multidrop 10BASE-T1S configurations, validating network stability and SPE channel performance before a final product design is finalized. Advanced technical support and customization services are available from Arrow's engineering solutions center (ESC). The 10BASE-T1S REF_SPE_T1S reference design is available now through Arrow. For more information, please visit https://www.arrow.com/
Microchip Technology has launched its SAM9X75D5M System-in-Package, an AEC-Q100 Grade 2-qualified hybrid microcontroller unit for automotive human-machine interfaces. The device targets applications including digital cockpit clusters, smart clusters for two- and three-wheelers, HVAC controls and EV chargers. The SiP features an Arm926EJ-S processor and 512 Mbit DDR2 SDRAM, supporting displays up to 10 inches at 1024 × 768 pixels with interfaces including MIPI DSI, LVDS and parallel RGB. The device combines microprocessor processing, high memory density and microcontroller functionality in one package, streamlining PCB design whilst reducing routing complexity. It also shields designers from discrete DDR memory supply volatility whilst balancing cost, performance and power efficiency.