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Synopsys

EDA software for chip design

Applications Engineering Senior Engineer

Solution EngineeringConfirmed live in the last 24 hours
Full-timeUnited States

About the Job

Requirements

  • A Master's degree in Electrical Engineering or Computer Science, or a Bachelor's degree in Electrical Engineering or Computer Science with at least 2 years of relevant experience as a circuit designer or CAD engineer.
  • A solid understanding of full custom and analog design flows, including schematic capture, layout, analog verification, and physical verification.
  • Hands-on experience with analog or mixed-signal simulation, ideally using SPICE, FastSPICE, or similar tools in a production design environment.
  • Scripting skills in TCL, Perl, or Python to automate workflows, debug customer setups, and build deployment solutions.
  • Strong communication skills to explain technical issues clearly to designers and summarize business impact for managers.
  • Willingness to travel for customer visits, training sessions, and on-site support as needed.
  • Ability to systematically investigate failing simulations, including checking netlist issues, model problems, and convergence settings.
  • Ability to ask clarifying questions to understand customer setups before proposing solutions.
  • Comfort presenting technical content to customers.
  • Ability to manage multiple customer requests and internal tasks while tracking commitments.
  • Ability to recognize when to escalate issues and when to investigate independently.
  • Commitment to thoroughly resolving customer issues and following through until solutions work.

Responsibilities

  • Lead technical evaluations and benchmarks for customers, demonstrating the Synopsys Custom Implementation Platform on their design challenges with guidance from senior team members.
  • Deploy analog simulation flows, including SPICE, FastSPICE, and mixed-signal simulation, for customer design teams working on custom digital, analog, RF, and memory blocks.
  • Debug simulation convergence issues, performance bottlenecks, and methodology gaps in customer environments, escalating issues beyond current expertise to senior engineers.
  • Demonstrate cloud-based analog design flows and show customers how to run complete custom implementation workflows through cloud infrastructure.
  • Deliver technical training sessions and provide on-site support to customer design teams, helping them adopt best practices across schematic, layout, analog verification, and physical verification.
  • Document customer issues and enhancement requests, and work with senior engineers to communicate them to research and development and product management.
  • Support pre-sales activities by partnering with sales teams to deliver methodology presentations and product demonstrations during competitive evaluations.
  • Resolve simulation and methodology issues that could delay customer tapeouts.
  • Deliver technical demonstrations and build trust with customer engineering teams during competitive evaluations.
  • Support customer adoption of Synopsys tools by smoothing deployment and answering questions before they become blockers.
  • Identify usability gaps and customer pain points in production environments and contribute to product improvements.
  • Build relationships with customer design teams and develop reusable methodologies and solutions for multiple customer engagements.

About the Company

Synopsys

EDA software for chip design

Synopsys provides software tools and services for electronic design automation (EDA), helping engineers design, simulate, verify, and optimize semiconductor chips and systems. Its products cover the full design flow, including RTL-to-gating synthesis, place-and-route, timing analysis, verification, and silicon validation, as well as software integrity solutions and hardware-assisted verification. Engineers use these tools to model, simulate, and validate complex chip designs before manufacturing, reducing bugs and improving performance. Compared with many competitors, Synopsys differentiates itself through its broad, end-to-end design toolchain, large ecosystem of IP and integration with simulation and modeling capabilities gained from its 2025 merger with ANSYS, and its global scale and support. The company aims to help designers push the boundaries of chip and system performance, accelerate time-to-market, and enable silicon-to-systems design across a wide range of industries.

Company size
10,001+
Company stage
IPO
Headquarters
Sunnyvale, CA
Founded
1986

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