Principal Engineer - Model Optimizations

We are looking for a Principal Engineer to own how models are optimized for serving across our entire accelerator fleet—NVIDIA and AMD alike.

DigitalOcean is the Inference Cloud. The Inference Platform team runs frontier open models in production on a heterogeneous GPU fleet, and the gap between a model that merely runs and a model that runs well is measured in millions of dollars of GPU time and in whether a customer's SLO is met. Closing that gap is this role.

You will own the model optimization discipline end to end: quantization strategy and its accuracy budget, kernel selection and authoring, attention and MoE execution, speculative decoding, and the parallelism layout that ties them together. You'll do it across model architectures that change every few months and across two vendor stacks with genuinely different performance characteristics—CUDA/Hopper/Blackwell on one side, ROCm/MI300-class and beyond on the other. The hard part is not making one model fast on one GPU. It's building the methodology, tooling, and upstream relationships that make every model fast on every GPU we buy, and doing it fast enough to launch a new model the week it drops.

What You'll Be Doing:

• Setting the technical strategy for model optimization across the fleet: which techniques we invest in, which we consume upstream, and how we decide
• Owning quantization end to end—FP8, FP4/MXFP4, INT8, weight-only schemes such as AWQ and GPTQ—including calibration methodology, the accuracy budget we're willing to spend, and the eval gates that enforce it
• Driving performance for modern architectures at the execution level: MoE routing and fused expert kernels, MLA and GQA attention variants, long-context and sliding-window attention, and the memory-movement patterns each implies
• Leading speculative decoding work (draft models, EAGLE/Medusa-class methods, n-gram and lookahead approaches) and the acceptance-rate tuning that determines whether it actually pays
• Writing and tuning kernels where upstream falls short—CUDA, Triton, CUTLASS, and their ROCm counterparts (HIP, Composable Kernel, hipBLASLt, AITER)—and knowing when not to
• Establishing how we choose parallelism layouts (TP, PP, EP, attention DP) per model, per GPU family, per traffic shape, and encoding that into something repeatable rather than tribal knowledge
• Building the benchmarking and regression infrastructure that makes optimization claims trustworthy: agent-shaped and long-context traffic distributions, TTFT/ITL/throughput measurement, and accuracy validation that runs before anything ships
• Making AMD a genuinely first-class target rather than a port, and driving the upstream work in vLLM, SGLang, and TensorRT-LLM required to get there
• Partnering with NVIDIA and AMD engineering teams on pre-silicon enablement, early-access hardware, and roadmap feedback
• Setting technical direction, mentoring senior and staff engineers, and representing DigitalOcean in upstream communities, at conferences, and in customer technical deep dives

What You'll Add to DigitalOcean:

• 12+ years in performance-critical systems, with substantial recent experience optimizing LLM inference in production
• Deep understanding of GPU architecture and the inference performance model: memory bandwidth vs. compute bounds, arithmetic intensity, kernel launch and scheduling overhead, and where prefill and decode differ
• Hands-on kernel-level experience on at least one vendor stack and the demonstrated ability and appetite to work across both—CUDA/CUTLASS/Triton and ROCm/HIP/CK
• Practical quantization expertise, including the judgment to know when a technique that benchmarks well will fail a customer's accuracy bar
• Familiarity with the internals of at least one major serving engine (vLLM, SGLang, TensorRT-LLM), sufficient to land non-trivial changes upstream
• Strong Python and C++/CUDA skills, and rigor in profiling with Nsight, rocprof, and equivalent tooling
• A measurement-first disposition: claims backed by reproducible benchmarks, with an understanding of how easily inference benchmarks mislead
• Excellent written and verbal communication, and experience leading cross-functional efforts spanning infrastructure, product, and customers

Bonus:

• Meaningful upstream contributions to vLLM, SGLang, TensorRT-LLM, PyTorch, Triton, or ROCm
• Experience bringing up a new accelerator family for production inference, including the unglamorous parts—numerics differences, missing kernels, immature libraries
• Experience with disaggregated prefill/decode serving and its interaction with parallelism and quantization choices
• Track record of same-week or day-zero enablement for newly released frontier open models
• Publications or patents in efficient inference, quantization, or GPU kernel design

Compensation Range: 

• $249,600 - $312,000
  • Non-sales roles: In addition to base salary, this role is eligible to participate in DigitalOcean’s annual bonus plan and may be eligible for a new hire equity grant, subject to plan terms and local eligibility. Bonus amounts depend on company and individual performance.
  • Sales roles (sales compensation eligible): In addition to base salary, this role may be eligible to earn incentive compensation under the applicable sales compensation plan and may be eligible for a new hire equity grant, subject to plan terms and local eligibility.

*This is a hybrid role

JR: 2026-8158

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