Principal Engineer
High-Speed IO Design / Integration
Posted on 11/30/2023
INACTIVE
SambaNova Systems

51-200 employees

Hardware for AI
Company Overview
SambaNova's mission is to enable the future of AI today by providing purpose-built deep learning solutions, delivered as a service and deployable in weeks rather than years to accelerate AI adoption and value creation.
AI & Machine Learning
Financial Services
Government & Public Sector

Company Stage

Series D

Total Funding

$1.1B

Founded

2017

Headquarters

Palo Alto, California

Growth & Insights
Headcount

6 month growth

1%

1 year growth

-10%

2 year growth

-1%
Locations
Palo Alto, CA, USA
Experience Level
Entry
Junior
Mid
Senior
Expert
CategoriesNew
Software Engineering
Requirements
  • BS or MS in EE, ECE or CS
  • 7+ years of experience in silicon development with 5+ years in high-speed IO
  • Experience with analog/mixed-signal design
  • Good understanding of transceiver building blocks like PLL, RX/TX equalizers, CDR architecture, serializers/deserializers
  • Experience with the PHY/physical layer electricals for one or more protocols like Ethernet, PCIe, CXL, HBM, and UCIe
  • Experience with IP integration related methodology and flows
  • Experience working with third-party vendors
  • Must have done at least one full cycle SOC design from concept, all the way to post-silicon bring-up and productization
  • Good leadership skills and ability to multi-task and thrive in a dynamic environment
Responsibilities
  • Be the domain expert on high-speed IO architecture and protocols for SOC/system definition
  • Drive adoption of the latest IO technology and evaluate performance/implementation tradeoffs
  • Evaluate third-party PHY to meet chip and system PPA requirements
  • Perform PHY integration with PCS/Controller/MAC and other subsystem components
  • Define high-speed IO implementation requirements for the package and system
  • Review system-level design choices, power delivery and SI/PI simulations for IO interconnects
  • Interface with IP vendors to resolve any PHY-related issues during pre- and post-silicon phases
  • Support the chip physical design team and provide clocking and timing guidelines
  • Take a leadership role in post-silicon bring-up of IO and memory subsystems
  • Define PHY boot-up initialization and reset flows
  • Perform system-level electrical debug and root-cause analysis through the bring-up, validation and production phases
Desired Qualifications
  • Design experience with ADC-based Serdes and PAM4 signaling
  • High-speed Serdes bring-up and characterization experience in the lab