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EdgeCortix

Fabless AI accelerator designer for edge

Physical Design Lead

Full-TimeUpdated on 10/23/2026
No salary listed
Senior, Expert
Bachelor's, Master's
Hyderabad, Telangana, India
In Person
Hardware EngineeringSilicon & ASIC Design

About the job

Requirements
  • A Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
  • At least 8 years of experience in physical design of complex SoCs, with strong expertise in synthesis, timing closure, and physical implementation.
  • Proven experience implementing RTL-to-GDSII using Synopsys and/or Cadence electronic design automation tools.
  • Strong expertise in static timing analysis, synthesis, floorplanning, clock tree synthesis, place and route, multi-mode multi-corner analysis, dynamic voltage and frequency scaling, and low-power implementation using Unified Power Format.
  • Experience with advanced technology nodes of 12 nm and below.
  • Strong scripting skills using Tcl, Python, and shell.
  • Experience working with external implementation teams or design service partners.
Responsibilities
  • Lead end-to-end physical implementation from RTL to GDSII for AI SoCs, chiplets, and hardened IP blocks, ensuring successful tape-out with optimal power, performance, and area.
  • Provide technical leadership to the Physical Design team and guide external implementation partners to ensure high-quality and timely project execution.
  • Drive synthesis, floorplanning, placement, clock tree synthesis, routing, static timing analysis, timing closure, and sign-off across multiple process, voltage, and temperature corners using Synopsys and Cadence tools.
  • Develop, maintain, and continuously improve physical design methodologies, implementation flows, automation, and best practices.
  • Evaluate standard cell libraries, implementation methodologies, and technology options to maximize power, performance, area, and implementation efficiency.
  • Optimize power, performance, and area through improvements in architecture, logic implementation, synthesis, floorplanning, routing, libraries, and technology selection.
  • Own power planning and analysis, including Unified Power Format implementation, power grid generation, IR-drop and electromigration analysis, power budgeting, and power integrity.
  • Develop and optimize implementation constraints using SDC and Tcl, perform timing analysis, resolve timing bottlenecks, and drive engineering change order implementation.
  • Define floorplanning strategies and hierarchical partitioning for complex SoCs and chiplet-based designs.
  • Collaborate with Architecture, RTL, Verification, DFT, and Product Engineering teams, providing continuous implementation feedback to improve system-level power, performance, and area.
  • Participate in early architecture studies, implementation feasibility analysis, power, performance, and area estimation, and power and area budgeting for future products.
  • Drive sign-off quality by reviewing implementation reports, timing, power, congestion, design rule checking and layout versus schematic readiness, and physical verification metrics.
  • Coordinate with external backend implementation partners, review deliverables, and ensure execution aligns with project milestones and quality standards.
  • Stay current with emerging semiconductor technologies, electronic design automation tools, and implementation methodologies, driving innovation and continuous improvement across the Physical Design flow.
  • Mentor and support junior engineers while fostering technical excellence within the Physical Design team.
Desired Qualifications
  • A Master's degree in Electrical Engineering or a related discipline.
  • 10–15 or more years of experience in Physical Design or SoC implementation.
  • Experience leading physical implementation for multiple tape-outs.
  • Experience with AI accelerators, chiplet architectures, or hierarchical SoC designs.
  • Strong understanding of design rule checking and layout versus schematic, IR-drop, electromigration, crosstalk, and physical sign-off.
  • Technical leadership, communication, mentoring, and cross-functional collaboration skills.

About the company

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EdgeCortix

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Website

EdgeCortix designs energy-efficient AI accelerators and software for edge computing in a fabless model, co-designing hardware and software to optimize AI performance on edge devices. Its main products are AI-specific processors and a software platform that, together, enable deploying AI at the edge with low power consumption. Unlike typical hardware vendors, EdgeCortix emphasizes software-centric co-design to maximize efficiency, aiming to deliver scalable edge intelligence for sectors like defense, robotics, and automotive. The company’s goal is to enable practical, power-conscious AI processing on edge devices, supporting broad deployment through its integrated hardware-software ecosystem and ongoing growth funded by investors.

Company Size

51-200

Company Stage

Debt Financing

Total Funding

$197M

Headquarters

Tokyo, Japan

Founded

2019

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Simplify Jobs

Simplify's Take

What believers are saying

  • September 24, 2026 RAIDEN launch gives EdgeCortix a fresh flagship product cycle.
  • EdgeCortix won Kawasaki's 2026-2028 aerial-defense program with several-million-dollar initial value.
  • April 2026 Axiro and MPower investment, plus Mizuho's ¥1.5 billion facility, extend runway.

What critics are saying

  • RAIDEN samples start early 2027; any tapeout slip delays revenue into 2028.
  • Kawasaki's several-million-dollar program cannot fund fabless chip development alone; customers must convert.
  • Missed power or thermal targets kill defense adoption and turn EdgeCortix into a science project.

What makes EdgeCortix unique

  • RAIDEN spans X1-to-X4 with one MERA stack, preserving software across deployments.
  • Kawasaki and Unigen validate a defense-plus-server niche few edge chip startups reach.
  • SAKURA-II cleared DIU, NASA heavy-ion, and U.S. Air Force flight testing in 2026.

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Benefits

  • Stock Options
  • Flexible Work Hours
  • Remote Work Options
  • Relocation Assistance

Growth & Insights and Company News

6 month growth

0%

1 year growth

0%

2 year growth

0%
IT Business Today
Oct 22nd, 2026
EdgeCortix, Unigen expand AI computing collaboration.

EdgeCortix, Unigen expand AI computing collaboration. Last updated: October 22, 2026 10:10 am EdgeCortix, a fabless semiconductor company specializing in energy-efficient artificial intelligence (AI), and Unigen Corporation, a global company that develops and manufactures enterprise and industrial electronics, announced that they have signed a Memorandum of Understanding (MoU) to expand their collaboration across product development, manufacturing, and market deployment, extending their cooperation to RAIDEN, a scalable computing platform designed for physical AI that EdgeCortix announced last month. This agreement further develops the partnership between the two companies, which already have a track record of product shipments. Unigen's "Amaretti" E1.S / E3.S AI modules, announced in April 2026, feature EdgeCortix's SAKURA-II AI accelerator and achieve 60 TOPS of AI performance with a power consumption of 10W. They support the use of generative AI in on-premise private environments, including language models and visual language models with over 20 billion parameters. Unigen's "Poundcake" servers equipped with Amaretti are currently available in configurations that can accommodate up to 24 AI modules with 32 GB of LPDDR4 memory. Poundcake and Amaretti have been deployed in call centers, medical networks, and telecommunications carriers, and are being used as a platform to support AI applications that support multiple channels. With this expanded collaboration, Unigen will expand its product lineup equipped with SAKURA-II and will design, manufacture, market, and sell next-generation E3.S modules and server computing products based on the RAIDEN platform. RAIDEN's performance varies not by product line, but by the number of dies. The 1-die, 2-die, and maximum 4-die configurations utilize a common hardware architecture and software stack, with the addition of dies expanding computing performance, memory capacity, memory bandwidth, and inter-die bandwidth. The 4-die RAIDEN configuration, through a common software stack, is designed to achieve over 3,300 TFLOPS of AI computing performance - more than 55 times that of the current SAKURA-II. Furthermore, it features up to 256 GB of memory, 548 GB/s of memory bandwidth, and up to 1.54 TB/s of inter-die bandwidth. This means that system development companies can continue to leverage their development assets. EdgeCortix's RAIDEN combines the DNA-X processor architecture with the common MERA(TM) software stack currently used in SAKURA-II, allowing for seamless transitions without rewriting models, tools, or application code. This means that the development achievements that Unigen and its customers have built up with Amaretti can be directly utilized in the successor platform. In addition to product development, the two companies plan to expand their collaboration to strengthen the market presence of their products in Japan, North America, Europe, and Asia. Unigen has the capability to handle a wide range of services, from product design and prototyping to new product mass production launch, mass production, supply chain management, assembly, testing, and after-sales service.

Nextronics Times
Sep 24th, 2026
EdgeCortix launches RAIDEN chiplet platform for Physical AI systems.

EdgeCortix launches RAIDEN chiplet platform for Physical AI systems. EdgeCortix has introduced RAIDEN, a scalable AI chiplet platform designed for high-performance artificial intelligence systems operating outside centralized data centers, where compute, memory, bandwidth and power constraints must be managed together. The Japanese fabless semiconductor company said RAIDEN is designed for what it calls "Physical AI" applications, including robotics, autonomous systems, aerospace and defense equipment, intelligent manufacturing and edge AI infrastructure. The platform scales from a single compute die to a four-die configuration while maintaining a common hardware and software architecture. At its maximum configuration, the RAIDEN X4 is architected to deliver up to 3.36 PFLOPS of FP4 AI compute, alongside up to 256GB of memory, 548GB/s of memory bandwidth and 1.54TB/s of aggregate die-to-die bandwidth. The platform also supports up to 6.4Tb/s of chip-to-chip connectivity, allowing systems to scale beyond an individual multi-die package. One architecture across three configurations. RAIDEN is built around a modular chiplet approach. EdgeCortix plans three configurations: the single-die X1, two-die X2 and four-die X4 flagship. The X1 and X2 configurations will be detailed in subsequent phases of the launch program. The X4 represents the highest-performance configuration disclosed by the company so far. All three versions use EdgeCortix's DNA-X accelerator architecture and MERA software stack. The company said this common platform is intended to allow customers to move between configurations without changing their underlying AI architecture or rebuilding software investments. | RAIDEN X4 specification | Up to | | AI compute | 3.36 PFLOPS FP4 | | Memory capacity | 256GB | | Memory bandwidth | 548GB/s | | Die-to-die bandwidth | 1.54TB/s | | Chip-to-chip scale-out connectivity | 6.4Tb/s | | Architecture | DNA-X | | Software stack | MERA | | Configuration | Four compute dies | | Power management | Configurable power settings | The architecture targets the "thick edge," a category of computing in which substantial AI processing takes place close to machines, sensors and operational environments rather than in centralized cloud infrastructure. This creates different requirements from conventional edge inference. Systems may need to process larger models, multiple workloads and real-time sensor data while operating within defined power, thermal and physical constraints. DNA-X expands beyond AI inference. At the core of RAIDEN is the latest version of EdgeCortix's DNA-X architecture. The company said the architecture retains runtime-reconfigurable capabilities from earlier generations while adding microcode-programmable matrix and vector engines. That design is intended to support workloads beyond conventional neural-network inference. EdgeCortix said perception, reasoning, application processing and control workloads can operate within the same platform. For Physical AI systems, this distinction is significant because an AI pipeline may involve multiple stages between sensing an environment and taking an action. A robotic or autonomous system, for example, can require perception, model execution, decision-making and control within a constrained operating environment. EdgeCortix said RAIDEN's architecture is intended to reduce system-level compromises associated with moving models and data between internal and external memory, aggressive quantization and dividing AI and non-AI processing across separate computing systems. The platform's memory and bandwidth scale with the number of compute dies, allowing the architecture to accommodate larger workloads as systems move from one configuration to another. MERA software links RAIDEN generations. Software portability is another component of the platform. The MERA software stack provides a common development and deployment environment across RAIDEN configurations, according to EdgeCortix. The company also said the software environment extends across product generations, allowing applications developed for its SAKURA-II platform to carry forward to RAIDEN. This approach is intended to reduce the software migration requirements associated with moving to a higher-performance hardware configuration. EdgeCortix Founder and CEO Dr. Sakyasingha Dasgupta said the company designed RAIDEN around the need for compute, memory, connectivity and software to scale together as Physical AI workloads evolve. "Physical AI will not be won by simply building a faster accelerator," Dasgupta said. "It requires a platform where compute, memory, bandwidth, connectivity and software scale together." Kawasaki, unigen among early customers. RAIDEN is entering the market with customer programs already secured, according to EdgeCortix. Kawasaki Heavy Industries Ltd. has selected RAIDEN-based solutions for multiple next-generation AI-enabled aerospace and defense products, the company said. Such applications can require computing platforms to operate within demanding system constraints while supporting workloads that may evolve during long product lifecycles. Unigen Corporation, a U.S.-based enterprise hardware provider, is developing RAIDEN-based server platforms. The work expands an existing collaboration between the companies involving SAKURA-II-powered modules and server systems, according to EdgeCortix. The engagements span two different deployment models: AI processing integrated into intelligent machines and higher-performance computing infrastructure designed for on-premise or edge environments. EdgeCortix said additional RAIDEN design wins, application categories and ecosystem partners will be disclosed as the program develops. Sampling starts in 2027. EdgeCortix expects customer sampling of RAIDEN to begin in early 2027, with volume production planned for the second half of 2027. The company has also opened its RAIDEN Early Access Program for qualified customers and ecosystem partners. Participants can engage with EdgeCortix during the development phase and receive priority consideration for customer samples. The launch places RAIDEN within a broader shift toward heterogeneous AI computing, where workloads are distributed across combinations of processors, accelerators, memory and specialized interconnects.

ICO Optics
Sep 24th, 2026
EdgeCortix and SpaceX to build orbital data centers.

EdgeCortix and SpaceX to build orbital data centers. By ICO Optics / September 23, 2026 This post contains affiliate links, and I will be compensated if you make a purchase after clicking on my links, at no cost to you. The intersection of commercial aerospace and artificial intelligence has reached a fascinating new frontier as tech innovators look to the stars for scalable computing solutions. Japanese startup EdgeCortix is setting its sights on a groundbreaking collaboration with SpaceX to design specialized semiconductor chips built explicitly for data centers deployed in outer space. By leveraging space-based platforms, this initiative seeks to process vast amounts of data directly in orbit while dramatically reducing latency for global networks. This strategy aligns with a broader industry push to bypass terrestrial power constraints by relocating heavy computing infrastructure straight into low Earth orbit. Table of Contents The mechanics of orbit-based computing infrastructure. EdgeCortix specializes in high-performance, energy-efficient artificial intelligence processors optimized heavily for demanding edge computing environments. Their proprietary technology is engineered to handle massive computational workloads while safely withstanding the harsh radiation conditions present in outer space. Overcoming severe engineering hurdles. Deploying server architecture beyond its atmosphere presents unique engineering hurdles, particularly regarding advanced thermal management and strict power supply constraints. Successfully securing a partnership with Elon Musk's aerospace venture would represent a monumental milestone for global chip designers looking toward the commercial space sector. If you want to keep up with the latest industry breakthroughs, check out its dedicated coverage of optics articles to see how hardware is evolving. Industry developments regularly influence how optical components and sensors integrate with advanced orbital processors. The future of real-time intelligence in space. Moving workloads off-planet helps alleviate the staggering energy demands currently straining power grids across the globe. Enthusiasts of high-tech gear can also explore various science toys that introduce younger generations to these revolutionary aerospace concepts. Ultimately, this type of pioneering collaboration paves the way for real-time AI processing capabilities integrated seamlessly into satellite constellations. As deep-tech startups continue forging alliances with aerospace leaders, the boundary between terrestrial infrastructure and celestial computing will continue to blur rapidly. Additional Reading:

HPCwire
Sep 24th, 2026
EdgeCortix unveils RAIDEN, a scalable, energy-efficient AI chiplet platform for Physical AI.

EdgeCortix unveils RAIDEN, a scalable, energy-efficient AI chiplet platform for Physical AI. September 24, 2026 Press play to listen to this content KANAGAWA, Japan, Sept. 24, 2026 - EdgeCortix has unveiled RAIDEN, its next-generation scalable AI chiplet platform purpose-built to address that challenge. Through this chiplet platform, RAIDEN carries EdgeCortix's energy-efficient design into a new performance class, scaling to meet the demands of Physical AI deployed outside centralized data centers. RAIDEN introduces a unified, energy-efficient architecture that scales from a single compute die to a four-die flagship within one hardware and software platform. At maximum scale, RAIDEN is architected to deliver up to 3.36 PFLOPS (3,360 TFLOPS) of FP4 AI compute, up to 256 GB of memory, 548 GB/s of memory bandwidth and up to 1.54 TB/s of aggregate die-to-die bandwidth, together with configurable power settings and up to 6.4 Tb/s of chip-to-chip scale-out connectivity for scaling beyond a single package. RAIDEN is entering the market with customer design wins already secured, spanning demanding Physical AI applications from next-generation aerospace and defense systems, robotic platforms, to high-performance edge AI servers. One Architecture. From One Die to Four RAIDEN is designed for Physical AI at the thick edge, an emerging class of high-performance AI systems deployed outside centralized data centers and closer to machines, sensors and operational environments. Rather than creating separate architectures for different performance classes, RAIDEN scales through a modular chiplet architecture: single-die (X1), two-die (X2) and the four-die (X4) flagship. All three configurations share EdgeCortix's latest DNA-X accelerator architecture and MERA software stack. Compute, memory capacity, memory bandwidth and inter-die bandwidth scale with the platform, allowing customers to address different performance, power and deployment requirements without moving to an entirely different AI architecture or software environment. This common architecture is designed to allow customers to move across RAIDEN configurations while preserving their software investment and application environment. Detailed specifications and deployment positioning for the X1 and X2 configurations will be introduced in subsequent phases of the RAIDEN launch program. Four Dies. One AI System to Run the Entire Workload At the top of the platform, the RAIDEN X4 flagship is architected to operate four compute dies as a tightly integrated system rather than as a collection of isolated accelerators. The RAIDEN X4 flagship configuration enables: * Up to 3.36 PFLOPS of FP4 AI compute * Up to 256 GB of memory * 548 GB/s of memory bandwidth * Up to 1.54 TB/s of die-to-die (DNA-X-to-DNA-X) bandwidth * Up to 6.4 Tb/s of chip-to-chip scale-out connectivity * Configurable power settings for different performance and deployment requirements * Integrated multi-core host processing per-die and high-speed system connectivity for self-contained designs As multimodal, generative, and agentic AI models become part of a diverse range of applications across the physical AI landscape, systems must simultaneously accommodate larger models, greater context, multiple concurrent workloads and increasingly demanding real-time constraints, all within practical system power envelopes. RAIDEN's scalable chiplet architecture is designed to address this continuum through a common platform, scaling heterogeneous compute, memory and connectivity from a single die to four dies while maintaining a common software environment. For applications that require additional system-level scale, RAIDEN's high-speed chip-to-chip connectivity provides up to 6.4 Tb/s of scale-out bandwidth, extending the architecture beyond an individual multi-die package. The architecture helps reduce the system-level compromises that increasingly constrain advanced Physical AI workloads: swapping models and data between internal and external memory, aggressive quantization, AI and non-AI workload partitioning, and the need to divide a single Physical AI pipeline across multiple discrete computing systems. Purpose-Built for AI That Perceives, Reasons and Acts Physical AI requires more than neural-network inference. Central to RAIDEN is the latest DNA-X architecture, engineered to execute the full workload while scaling the system as a unified platform. It maintains the runtime-reconfigurable advantages of earlier generations while introducing micro-code programmable matrix and vector engines. This innovation extends versatility beyond standard neural-network inference, providing the necessary support for perception, reasoning, application processing and control workloads to operate together within a common scalable platform. A single MERA software stack provides a common development and deployment environment across the RAIDEN family, allowing models, tools and software investments to carry across different platform configurations. The same stack spans EdgeCortix product generations, so work done on SAKURA-II today carries forward to RAIDEN rather than being rebuilt. "Physical AI will not be won by simply building a faster accelerator. It requires a platform where compute, memory, bandwidth, connectivity and software scale together - and where the hardware deployed today can run the models customers adopt years from now," said Dr. Sakyasingha Dasgupta, Founder and CEO of EdgeCortix. "That is what we built RAIDEN to do. One architecture and one software platform scaling from a single die inside an intelligent machine to a four-die flagship for the most demanding Physical AI workloads. Most importantly, customers are already designing around RAIDEN." RAIDEN extends EdgeCortix's vision of Powering AI That Acts beyond traditional edge inference into a broader class of Physical AI systems, spanning robotics and autonomous systems, intelligent manufacturing, telecommunications, aerospace and defense, and edge AI infrastructure. Availability and RAIDEN Early Access Program Customer sampling is expected to begin in early 2027, with volume production planned for the second half of 2027. The RAIDEN Early Access Program is now open, giving qualified customers and ecosystem partners an opportunity to engage with EdgeCortix during the development program and receive priority consideration for customer samples. The program has already generated strong customer interest, building on the design wins secured to date. RAIDEN, EdgeCortix next-generation chiplet solution, is based on results obtained from the project, 'Research and Development Project of the Enhanced Infrastructures for Post-5G Information and Communication Systems' (JPNP20017), subsidized by the New Energy and Industrial Technology Development Organization (NEDO). About EdgeCortix Inc. EdgeCortix is a fabless semiconductor company delivering energy-efficient AI compute across edge and Physical AI applications, from embedded devices to on-premise systems. Headquartered in Kanagawa, Japan, with operations in the United States and India, the company develops advanced silicon and software platforms built on its patented hardware-software co-design approach. Its Dynamic Neural Accelerator (DNA) architecture and MERA software stack support inference, generative and agentic AI workloads on one runtime-reconfigurable platform that scales from the SAKURA-II single-chip accelerators to the RAIDEN multi-die chiplet platform. EdgeCortix solutions serve robotics and autonomous systems, aerospace and defense, intelligent manufacturing, telecommunications and edge AI infrastructure, markets that demand real-time performance, energy efficiency and adaptability. "AI will kill us all." That's the mantra we've heard repeatedly this month from researchers... One neocloud traversing the AI inference landscape that you might want to keep an eye... For the past couple years, companies have been treating the high demand and explosive growth... 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Nikkei Asia
Sep 23rd, 2026
EdgeCortix unveils AI chip for factories and space data centers with SpaceX partnership

Japanese government-backed semiconductor startup EdgeCortix has unveiled its latest chip designed for physical AI, targeting deployment on factory floors and in space. The Palo Alto-based company aims to collaborate with SpaceX on space data centre chips. The new chip is specifically designed for physical AI applications. EdgeCortix is exploring opportunities beyond traditional industrial settings, seeking to extend its technology into space-based operations through a potential partnership with SpaceX. The startup's focus on space data centres represents an emerging frontier for semiconductor applications, combining advanced chip design with the growing demand for processing capabilities in orbit.