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Astera Labs

Designs chips that connect data center systems

Principal Electrical Engineer - Smart Cable Modules

Board & Electronics DesignConfirmed live in the last 24 hours
Full-timeSan Jose, CA, USAIn-person

About the Job

Requirements

  • A Bachelor's or Master's degree in electrical engineering or a closely related field.
  • 10–12+ years of progressive electrical engineering experience, including at least 5 years focused on high-speed SerDes-based interconnect, active copper cable, or optical/pluggable module products.
  • A track record of architecting and delivering production hardware with 56G/112G or faster SerDes interfaces, such as Ethernet, PCIe, or InfiniBand.
  • Expert-level understanding of signal integrity principles, including impedance control, differential-pair management, eye-mask budgeting, and channel-loss allocation, sufficient to author design rules and review layouts without full SI simulation.
  • Proficiency with industry-standard schematic capture tools such as Cadence Allegro or OrCAD and PCB layout review.
  • Deep familiarity with OSFP, QSFP-DD800, and SFP-DD MSA mechanical, electrical, and management specifications.
  • Hands-on experience with CMIS 5.x, SFF-8636 module management, and I2C/MDIO interface design.
  • Ability to lead hardware bring-up and debug complex mixed-signal failures using high-bandwidth oscilloscopes and protocol analyzers.
  • Strong power-delivery-network design fundamentals, including multi-rail sequencing, transient response, decoupling strategy, and thermal-electrical co-analysis.
  • Experience interfacing with silicon vendors or teams on reference-design customization, silicon errata management, and platform bring-up.

Responsibilities

  • Define and own the end-to-end electrical architecture for smart cable modules, including SerDes channel topology, power-delivery strategy, and thermal budgeting for multi-gigabit 112G PAM4 and 56G NRZ designs.
  • Establish and maintain internal electrical design standards, PCB layout rules, and signal-integrity/power-integrity guidelines for the broader hardware team.
  • Lead architecture, schematic, layout, and DVT technical reviews, and provide authoritative sign-off on high-speed digital designs.
  • Contribute to the module hardware roadmap in alignment with host ASIC platform generations, MSA form-factor evolution, and customer requirements.
  • Evaluate and select components, and engage directly with supplier engineering teams on reference-design adaptation and silicon bring-up support.
  • Drive schematic capture and PCB design for complex multilayer modules housing multi-gigabit SerDes retimer or DSP ASICs in thermally and spatially constrained OSFP/QSFP-DD enclosures.
  • Own power-delivery design, including multi-rail regulation, hot-plug sequencing, brownout protection, and inrush management within MSA-defined power envelopes.
  • Review and recommend PCB stack-up, impedance targets, via structures, and differential-pair routing rules; review and approve layout execution with sufficient signal-integrity understanding to ensure first-pass compliance.
  • Define module-management hardware architecture, including I2C topology, register-map implementation, microcontroller selection, and diagnostic-monitoring interface circuitry.
  • Perform analog and mixed-signal subcircuit design, including clock distribution, oscillator selection, ESD protection, and supervisory logic.
  • Author or co-author hardware bring-up strategies, debug plans, and acceptance-test procedures for new module designs; lead or directly execute board bring-up.
  • Oversee firmware integration testing, control-interface validation, and module diagnostic-monitoring verification.
  • Lead root-cause analysis on complex hardware failures, review failure-analysis reports, and implement changes.
  • Define and champion DFT/DFM strategies with contract manufacturers and PCB fabrication partners to improve yield and reduce manufacturing cost.
  • Collaborate with firmware and software teams to define initialization sequences, power-management schemes, and real-time diagnostic algorithms.
  • Represent the organization in relevant MSA and IEEE standards working groups and influence specification development in support of product strategy.
  • Mentor and technically develop senior- and mid-level engineers, elevating the hardware team's collective capabilities in high-speed design.
  • Contribute to strategic hiring, technical onboarding, and department-level engineering process improvement.

Desired Qualifications

  • Experience at the architecture or lead-engineer level on 800G or beyond module programs.
  • Familiarity with co-packaged optics (CPO) or linear-drive (LPO) module electrical architecture.
  • Working knowledge of host-side switching ASIC electrical interfaces and SerDes equalization schemes.
  • Participation in OIF, IEEE 802.3, or QSFP/OSFP MSA standards bodies.
  • Experience with PCIe Gen 5/6 retimer module designs.
  • Python scripting for lab automation, measurement-data reduction, or hardware-characterization workflows.

About the Company

Astera Labs

Designs chips that connect data center systems

Astera Labs designs chips and hardware modules that move data between processors, memory and accelerators in data centers. Its customers include cloud providers, chip vendors and equipment makers building servers and large computing clusters for AI and other workloads. Retimers restore signal quality, switches connect devices and memory controllers expand the memory available to computing systems, while COSMOS software monitors and manages these links. The company sells its products directly and through distributors, using outside manufacturers to fabricate and assemble its hardware. Astera Labs was founded in 2017 and is headquartered in San Jose, California.

Company size
501-1,000
Company stage
IPO
Headquarters
San Jose, CA
Founded
2017

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