Power Validation Engineer
No salary listed
Mid
Bachelor's, Master's
San Jose, CA, USA
In PersonFully in-person in San Jose; relocation support is available for those moving to San Jose.
Hardware EngineeringHardware Validation & Testing
About the job
Requirements
- A bachelor's degree in Electrical Engineering or a related field.
- Deep understanding of ASIC and system-level power delivery, including voltage regulator module topology, power delivery network impedance, decoupling strategy, and transient response, with hands-on bench experience using precision shunts, isolated differential probes, and vector network analyzer-based power delivery network impedance measurement.
- Expertise with multi-phase solutions with high dynamic content and low tolerance.
- Experience tuning voltage regulators to a well-defined power test plan to ensure voltage regulator specifications meet central processing unit and ASIC requirements.
- Ability to design experiments that isolate root cause in a complex hardware-software stack, strong oscilloscope and laboratory instrument fluency, including triggering on rare transient events and correlating multi-channel captures, and a track record of finding bugs that surface only under specific workload or environmental conditions.
- Relevant experience with silicon bring-up.
Responsibilities
- Design and execute power measurement campaigns across all voltage rails under realistic large language model inference and power virus workloads; characterize peak, sustained, and idle power envelopes across process, voltage, and temperature corners and define derating curves used in system thermal and power delivery network specifications.
- Validate power delivery network performance, including voltage regulator module load-step response, Peripheral Component Interconnect Express power compliance, and power delivery network impedance, and translate measurements into feedback on capacitor placement, plane geometry, and decoupling strategy for printed circuit board and package design teams.
- Profile power transient events and correlate them with on-die performance monitor data; build automated power-sweep frameworks exercising inference workloads across model sizes, batch sizes, sequence lengths, and precision modes.
- Run extended continuous stress workloads to surface reliability risks and throttling behavior; instrument multi-zone thermal profiles and support overseas partners with system-level testing, production, and debugging.
- Validate power sequencing, PMBus telemetry accuracy, and baseboard management controller alert thresholds across cold-start, hot-restart, and fault-injection scenarios; own power-related pass/fail criteria across FAT, SFT, and RIN qualification stages.
- Feed characterization data back to register-transfer-level and physical design teams as input for dynamic voltage and frequency scaling policy, clock-gating coverage, and leakage optimization; write validation reports that enable silicon and firmware teams to act without repeating experiments.
- Lead the electrical characterization, validation, and qualification process for the on-board system-level power distribution network, spanning power converter design through ASIC power integrity validation.
- Support design engineers through debugging, component validation, and failure analysis for released products; troubleshoot independently and determine the root cause of electrical component defects and design flaws.
- Develop and implement automated and scripted test procedures for qualification and testing of devices under test as part of a comprehensive automation suite.
- Collect, analyze, and aggregate test data to support engineering decisions, generate reports on findings, reduce data sets, and investigate test outcomes down to the hardware interface or component level.
- Collaborate with hardware designers and diagnostics development teams to understand project architectures and system components and ensure necessary support for testing and debugging is implemented.
Desired Qualifications
- Advanced degrees or certifications in power electronics or related areas.
- A master's degree in Power Electronics.
- Experience with high-voltage testing at 800 volts or higher.
- Prior power validation work on artificial intelligence accelerators, graphics processing units, or high-performance server platforms, including high-bandwidth memory power characterization or memory power management interfaces.
- Experience with OpenBMC, IPMI, or custom baseboard management controller firmware for sensor monitoring and power capping; familiarity with large language model inference stacks such as vLLM or TensorRT-LLM sufficient to construct representative power workloads.
- Proficiency in Python for test automation, data pipeline construction, and statistical analysis; experience debugging from PMBus register dumps and baseboard management controller sensor logs through firmware traces and Linux kernel power management.
About the company
Etched designs AI chips and the server racks built around them for AI companies and cloud providers, focusing only on inference, the work of running trained models to answer requests. In 2024, it unveiled a chip hard-wired to run only transformers, the type of AI model behind ChatGPT, after betting at its founding that they would dominate AI. Etched develops its chips, racks, and software together, and each rack links many chips through a shared pool of fast memory so very large models with long inputs can answer quickly. It earns money by selling these complete systems rather than individual chips. Etched was founded in 2022 and is based in San Jose, California.
Company Size
201-500
Company Stage
Series D
Total Funding
$1.6B
Headquarters
San Jose, California
Founded
2022
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Simplify's Take
What believers are saying
- Equity is gaining value: Etched's valuation jumped from $5 billion in December 2025 to $21 billion in August 2026.
- Room to grow: Etched's 110 open roles in October 2026 equal over a quarter of its roughly 400-person staff.
- Colleagues include chip veterans: about 15% of Etched's employees came from Nvidia, the biggest maker of AI chips.
What critics are saying
- A rival is further along: chipmaker Cerebras had $510 million in 2025 sales before its $5.5 billion May 2026 IPO.
- Delivery has barely begun: Etched announced its first rack shipment in August 2026 against over $1 billion in orders.
- Expect to be on-site: 93% of Etched's October 2026 job posts describe a fully in-person team.
What makes Etched unique
- Its chips run on less power: Etched runs chip math at under half the voltage of most AI chips.
- It runs its own production: Etched opened a Taiwan factory and an 80,000-square-foot facility near its San Jose base.
- Trading firms back it: Jane Street, Hudson River Trading and Two Sigma invested, and Jane Street is its first customer.
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Benefits
- Health Insurance
- Dental Insurance
- Vision Insurance
- Unlimited Paid Time Off
- Flexible Work Hours
- Remote Work Options
- Paid Vacation
- Paid Sick Leave
- Paid Holidays
- Hybrid Work Options
- Stock Options
- Company Equity