ASIC Digital Design Tech Lead

The application window is expected to close on: 01/18/2027<h2>Meet the Team</h2><p>The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.</p><br /><h2>Your Impact</h2><p>As a Digital Design Technical Leader for Silicon One Optics, you won’t just be building chips—you will architect the backbone of next-generation optical interconnects. From initial concept to tapeout and post-silicon production, you will own the full ASIC lifecycle and lead cross-functional engineering teams across digital, analog, firmware, and physical design.</p><br /><p>In this high-stakes role, you will define digital architectures, spearhead the integration of cutting-edge high-speed IPs (ODSP, D2D IP, SerDes XSR/PAM4), and optimize power and performance for 100G, 200G, and 400G silicon photonics and Co-Packaged Optics. This is your opportunity to drive technical strategy, pioneer breakthrough interconnect innovations, and deliver silicon that powers the future of high-performance computing.</p><br /><ul><li>End-to-End Silicon & Subsystem Design: Lead individual design contributions from pre-silicon RTL through GDS2 signoff and post-silicon bring-up (FPGA prototyping, lab validation, and ATE) for complex digital blocks and CPU subsystems.</li><li>Architecture & Specification: Translate top-level requirements into high-speed datapath and low-speed control plane block specifications—balancing power, timing, loop dynamics, and hardware/firmware trade-offs.</li><li>Verification & IP Integration: Independently simulate and debug complex design issues, sign off on verification coverage, and support the integration of SerDes and DSP IPs.</li><li>Backend Implementation & Automation: Support synthesis, DFT, low-power design, and timing closure while developing automation scripts to process Quality of Results (QoR) metrics.</li><li>Cross-Functional Collaboration: Partner seamlessly with cross-functional teams to resolve technical design challenges and maintain system stability.</li></ul><br /><h2>Minimum Qualifications</h2><ul><li>Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience</li><li>Prior digital design experience working with FSMs, CPU sub-systems, complex SoCs, and FPGA validation,</li><li>Prior experience in managing the complete ASIC/SoC design flow</li><li>Prior experience with key bus and interface protocols (e.g., SPI, I2C, APB, AXI) as well as high-speed SerDes, Ethernet, and D2D PHY IP.</li></ul><br /><h2>Preferred Qualifications</h2><ul><li>End-to-End Silicon Lifecycle & Architecture: Prior experience leading the architecture and design of complex digital blocks and CPU subsystems from pre-silicon RTL to GDS2 signoff, through post-silicon FPGA prototyping, lab validation, and ATE bring-up.</li><li>Specification & Microarchitecture Design: Prior experience developing top and block-level specifications for high-speed datapath and low-speed control planes, including power/timing budgeting, feedback/control system stability, and hardware vs. firmware trade-offs.</li><li>Verification, Simulation & IP Integration: Prior experience reviewing verification coverage metrics, independently debugging verification issues, supporting firmware-based verification/architecture, and integrating SerDes and DSP IP.</li><li>Implementation, Backend & Automation: Hands-on experience with backend implementation activities—including synthesis, timing closure, DFT, low-power design, design automation scripting, and QOR metric processing.</li><li>Cross-Functional Leadership: Prior experience collaborating across cross-functional engineering teams to resolve technical trade-offs and complex design issues.</li></ul><p> </p><p></p><h1>Why Cisco? </h1><p>At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.</p><p>Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. </p><p>We are Cisco, and our power starts with you. </p><p></p><h1>Message to applicants applying to work in the U.S. and/or Canada:</h1><p></p>The starting salary range posted for this position is $166,300.00 to $238,300.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.<p></p><p>Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.</p><p></p><p>U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks.  Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.</p><p></p><p>U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:</p><ul><li><p>10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees</p></li><li><p>1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco</p></li><li><p>Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees</p></li><li><p>Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)</p></li><li><p>80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next</p></li><li><p>Additional paid time away may be requested to deal with critical or emergency issues for family members</p></li><li><p>Optional 10 paid days per full calendar year to volunteer</p></li></ul><p></p><p>For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.</p><p></p><p>Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:</p><ul><li><p>.75% of incentive target for each 1% of revenue attainment up to 50% of quota;</p></li><li><p>1.5% of incentive target for each 1% of attainment between 50% and 75%;</p></li><li><p>1% of incentive target for each 1% of attainment between 75% and 100%; and</p></li><li><p>Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.</p></li></ul><p></p><p>For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.</p><p></p><p>The applicable full salary ranges for this position, by specific state, are listed below:</p><p></p><p>New York City Metro Area:</p>$186,900.00 - $307,800.00<p></p><p>Non-Metro New York state & Washington state:</p>$166,300.00 - $274,100.00<p></p><p>* For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.</p><p>** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.</p>