Quest Global

Engineering services, digital transformation, asset management

Physical Design Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours

Full-timeBengaluru, Karnataka, IndiaNo salary listedIn-person

About the Job

Requirements

Strong understanding of ASIC/SoC design flow.
Hands-on experience with floorplanning and placement, clock tree synthesis and routing, static timing analysis, and power analysis including IR and electromigration.
Good knowledge of process technologies such as 7nm, 14nm, and 28nm, and signal integrity and crosstalk.
Scripting skills in Tcl, Python, or Shell.
Experience with Synopsys tools including ICC2, PrimeTime, and Fusion Compiler; Cadence tools including Innovus, Tempus, and Voltus; and Mentor Graphics tools including Calibre DRC/LVS.
Bachelor’s or Master’s degree in Electronics, VLSI, or Electrical Engineering.
2–10 years of experience in physical design, depending on seniority.

Responsibilities

Perform floorplanning, placement, clock tree synthesis, and routing.
Handle timing closure, including static timing analysis and setup and hold fixes.
Work on power optimization and IR drop analysis.
Perform physical verification, including DRC, LVS, and ERC.
Execute ECO implementation and convergence.
Collaborate with RTL, DFT, and STA teams for design closure.
Analyze and fix congestion, signal integrity, and noise issues.
Ensure the design meets foundry and sign-off requirements.
Achieve timing closure by resolving setup and hold violations.
Optimize power and area.
Deliver designs that are clean for DRC and LVS.
Deliver projects on time and maintain tape-out quality.

Desired Qualifications

Experience with advanced nodes at or below 16nm.
Knowledge of low-power design techniques such as UPF and CPF.
Exposure to DFT and chip-level integration.
Experience with multiple tape-outs.

Job Requirements a { text-decoration: none; color: #464feb; } tr th, tr td { border: 1px solid #e6e6e6; } tr th { background-color: #f5f5f5; }Key Responsibilities<ul><li>Perform floorplanning, placement, clock tree synthesis (CTS), and routing</li><li>Handle timing closure (STA) including setup and hold fixes</li><li>Work on power optimization and IR drop analysis</li><li>Perform physical verification (DRC, LVS, ERC)</li><li>Execute ECO implementation and convergence</li><li>Collaborate with RTL, DFT, and STA teams for design closure</li><li>Analyze and fix congestion, signal integrity, and noise issues</li><li>Ensure design meets foundry and sign-off requirements</li></ul>Required SkillsTechnical Skills<ul><li>Strong understanding of ASIC/SoC design flow</li><li>Hands-on experience in:<ul><li>Floorplanning & Placement</li><li>CTS & Routing</li><li>Static Timing Analysis (STA)</li><li>Power analysis (IR/EM)</li></ul></li><li>Good knowledge of:<ul><li>Process technologies (7nm / 14nm / 28nm etc.)</li><li>Signal integrity & crosstalk</li></ul></li><li>Scripting skills:<ul><li>Tcl / Python / Shell</li></ul></li></ul>Tools Experience<ul><li>Synopsys (ICC2, PrimeTime, Fusion Compiler)</li><li>Cadence (Innovus, Tempus, Voltus)</li><li>Mentor Graphics tools (Calibre DRC/LVS)</li></ul>Qualifications<ul><li>Bachelor’s or Master’s degree in Electronics / VLSI / Electrical Engineering</li><li>2–10 years of experience in physical design (based on seniority)</li></ul>Preferred Skills<ul><li>Experience in advanced nodes (≤16nm)</li><li>Knowledge of low-power design techniques (UPF/CPF)</li><li>Exposure to DFT and chip-level integration</li><li>Experience in multiple tape-outs</li></ul>Key Performance Indicators (KPIs)<ul><li>Timing closure (setup/hold violations)</li><li>Power and area optimization</li><li>Design rule clean (DRC/LVS clean)</li><li>On-time project delivery</li><li>Quality of tape-out</li></ul>

About the Company

Quest Global

Engineering services, digital transformation, asset management

QuEST Global provides engineering and lifecycle services across aerospace, automotive, energy, healthcare, and transportation, focusing on digital transformation and asset management. It uses edge computing, cloud, AI/ML, and industrial IoT to deliver tailored engineering solutions through long-term partnerships, service contracts, project-based engagements, and strategic collaborations. It differentiates itself with a broad industry footprint, global delivery model, and emphasis on partnerships, talent development, and workplace culture. Its goal is to help clients improve operational efficiency and drive business growth by transforming engineering processes and assets with digital tools and data-driven management.

Company size: 10,001+
Company stage: Growth Equity (Venture Capital)
Total funding: $581M
Headquarters: Greenville, SC
Founded: 1997

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