Innovation Lab Intern

SanDisk (SNDK) and Kioxia's 9th-generation QLC NAND: A 33% faster die that adds no bits. August 12, 2026 Kioxia and SanDisk announced their 9th-generation 2Tb QLC 3D flash memory on August 12, eight days after the same two companies unveiled their 10th-generation QLC technology at the Future of Memory and Storage conference in Santa Clara. The ordering is not a clerical error, and it is the most useful fact in the release. The 10th generation is a node advance: 332 layers, better than 37 Gb/mm[2], roughly 60 percent more bits per unit area than the 8th generation now in mass production. The 9th generation is not a node advance at all. It bonds an advanced CMOS wafer to the existing memory-array platform, which is to say the same cell array already running in the 8th-generation 2Tb QLC die, and pulls out a 4.8 Gb/s NAND interface, a 33 percent improvement, plus a six-plane architecture, higher read and write bandwidth, and better power efficiency on both paths. Bit density does not move. Hideshi Miyajima said the quiet part in the first quote of the release: the approach delivers high performance while keeping investment costs relatively low. That sentence is the product. The mechanism is CBA, the CMOS-directly-Bonded-to-Array process the two companies have been building toward since ISSCC 2025. Logic and array are fabricated on separate wafers under separately optimized conditions and joined with wafer-to-wafer alignment. Everything that determines how fast a NAND die talks to a controller lives on the logic side: page buffers, sense amplifiers, the I/O ring, and the plane-control circuitry that decides how many operations a die can run in parallel. In a conventional CMOS-under-array or CMOS-over-array layout, adding planes means spending array silicon on periphery, which means fewer die per wafer. You pay for speed in bits. Under CBA the periphery has its own wafer on its own node, and the plane count goes up against a supply of mature logic wafers rather than against NAND array area. Logic wafers are not what is scarce right now. Plane count is also the specific thing QLC has always needed. Four-level cells were never short on density; they were short on parallelism, which is why QLC spent most of a decade confined to read-heavy nearline tiers where it competed with disk rather than with TLC. A 2Tb die that cannot serve enough concurrent reads is a tape substitute with better marketing. Six planes and a 4.8 Gb/s interface are what make a QLC die viable behind inference pipelines that hammer model weights, KV caches and vector indices on the read path all day. This is the same reasoning that produced the 122.88TB LC9 class of drive on the 8th-generation 2Tb QLC die, except that the constraint being relieved this time is bandwidth rather than capacity. For anyone positioned in the memory complex, the important thing is what this announcement is not. The market has been trained by four decades of NAND cycles to read a flash technology release as a bearish supply signal: more layers, more bits per wafer, eventual glut, cycle over. The 9th generation inverts that reflex. It adds no bits. The array is the same array, the wafer output is the same wafer output, and the only thing that changes is the performance tier and therefore the price of capacity that was already committed. That is a mechanism for raising realized ASP without loosening supply by a single die. In a market where the shortage is being sustained by exited and redirected capacity rather than by demand alone, and where the two Korean producers have chosen capital returns over the capex that would end it, a technology that improves the product without improving the bit count is exactly the wrong kind of progress for anyone short memory. The moat here is manufacturing, not cells. Layer count is a treadmill with published finish lines; everyone arrives at 300-plus eventually and the ranking resets each generation. What CBA buys is the decoupling of two development schedules that are otherwise welded together. Kioxia and SanDisk can advance CMOS on one clock and the array on another and then ship the cross-product as a saleable generation. That is the only reason a 9th generation exists at all: it is a product assembled out of the seam between two roadmaps rather than a step along either one. It also functions as a hedge. If the 332-layer 10th generation yields slowly or ramps late out of the Kitakami K2 build, there is now a high-performance QLC part sitting on a proven array that can be sold into the same sockets in the meantime. The nearest architectural analog anyone has is YMTC's Xtacking, and YMTC's access to leading-edge equipment is constrained by export controls. Samsung, SK Hynix and Micron are all working toward bonded periphery; none of them is shipping a generation defined by it. The capital-efficiency argument compounds the one already visible in the financials. SanDisk carried $674 million of net property, plant and equipment against $20.2 billion of annual revenue in fiscal 2026 because the fabs sit inside the Kioxia joint venture. A performance upgrade that consumes logic wafers instead of NAND array capacity is the same structural advantage expressed one layer further down: SanDisk gets to sell a faster part without owning the tool that makes it faster. The stock has been trading as though price, not volume, is the variable that matters, which is correct. SNDK changed hands near $1,280 on the session, up roughly 3 percent, with Kioxia Holdings up close to 4 percent in Tokyo. That leaves the shares about 46 percent below the June 25 record of $2,354.39 and down roughly a quarter since mid-July, despite a fiscal Q4 that beat on EPS by 13.5 percent on $8.97 billion of revenue and guidance implying more than 350 percent year-over-year growth into September. Consensus sits at a $2,053.50 twelve-month target across 23 analysts with no sell ratings, a $3,000 high and a $1,000 low, a spread wide enough to concede that nobody is really underwriting the memory cycle so much as ranking their confidence in how long it runs. Argus upgraded on August 10. The drawdown since July is a bet that NAND pricing rolls over. Today's release is the counter-argument, and it costs the companies almost nothing to make. The decision-relevant thing to watch is not the layer count on the 10th generation. It is whether the 9th-generation die shows up in a qualified hyperscaler SKU, and at what capacity point relative to the drives already built on the 8th-generation 2Tb QLC. If the same drive families reappear at 4.8 Gb/s on the same array, SanDisk will have repriced its existing capacity footprint without expanding it. Qualification announcements, not roadmap slides.

SK hynix has effectively become the largest shareholder of Japanese NAND flash manufacturer Kioxia. According to documents filed with the Tokyo Stock Exchange on 10 January, Bain SPC2, an investment vehicle established by Bain Capital, now holds 14.19% of Kioxia, surpassing previous largest shareholder Toshiba at 14.12%. SK hynix holds convertible bonds in Bain SPC2 that grant it full voting rights, making it Kioxia's de facto largest shareholder. The South Korean chipmaker invested JPY395bn in the SPC as part of Bain Capital's 2018 acquisition consortium for Kioxia. However, SK hynix cannot currently exercise voting rights. The company agreed not to hold more than 15% of Kioxia's voting rights until 2028 without consent. Kioxia has flagged the situation as a risk factor, citing potential conflicts of interest with the competitor.

Kioxia Corporation's KIOXIA GP Series PCIe NVMe SSD has won the "Best of Show" award in the Specialized Storage category at FMS: the Future of Memory and Storage 2026. The KIOXIA GP1 PCIe 6.0 SSD is the industry's first Super High IOPS SSD optimised for GPU direct access, purpose-built for AI infrastructure. Powered by KIOXIA XL-FLASH generation 2 low-latency flash memory, it delivers up to 10 million random read IOPS with 512-byte data access. The technology enables flash to serve as a high-performance memory extension tier, helping improve GPU utilisation for AI workloads by extending High Bandwidth Memory with a flash tier. The architecture is designed to scale from 10 million random read IOPS to future generations targeting 100 million IOPS. Evaluation samples will be available to select customers by the end of 2026.