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Cerebras

AI accelerator hardware replacing GPUs

Principal Network Systems Architect

Hardware Systems IntegrationConfirmed live in the last 24 hours
Full-timeSunnyvale, CA, USANo salary listedHybrid

About the Job

Requirements

  • A BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • Typically 12 or more years of relevant industry experience, including principal-level technical ownership of a major networking, switching, accelerator, or high-performance computing system from architecture into implementation or deployment.
  • Deep expertise in low-latency or proprietary interconnects, fabric protocols, switch architecture, or a closely related area, with enough data-plane depth to reason about switch pipelines, buffering, routing, flow or congestion control, and reliability.
  • Experience deriving network requirements from incomplete workload and system information, with the range to make decisions across software, accelerator I/O, topology, and physical constraints.
  • Working knowledge of Ethernet, IP, and RDMA, plus conceptual familiarity with BGP and EVPN and the tradeoffs between routed networks and simpler low-latency scale-up designs.
  • Architectural judgment grounded in prior implementation, modeling, silicon, lab, bring-up, or debugging work.
  • A record of making clear technical decisions and influencing engineering leaders, implementation teams, suppliers, and customers.

Responsibilities

  • Set the multi-generation architecture and roadmap for Cerebras scale-up networks and their interfaces to scale-out and customer-facing networks.
  • Work with application, compiler, runtime, and communication-library teams to understand mapping and communication choices, then derive the required bandwidth, latency, ordering, availability, and serviceability.
  • Define fabric topology, protocols, and switch behavior, including routing, buffering, flow control, reliability, and fault containment, and connect data-plane choices to end-to-end system behavior.
  • Decide when to use standards-based technology or merchant silicon and when a custom protocol, switch, link, or offload is justified.
  • Use performance models, traffic simulation, prototypes, and lab data to test architecture choices and set acceptance criteria.
  • Write architecture and interface specifications, lead design reviews, and drive cross-layer decisions through implementation, bring-up, and qualification.

Desired Qualifications

  • Experience with proprietary accelerator interconnects or scale-up technologies such as NVLink, xGMI, TPU ICI, Xe Link, or UALink-class systems.
  • Experience with switch ASICs, NICs or DPUs, accelerator I/O, transport offload, collective acceleration, coherent memory, or custom-fabric work.
  • FPGA architecture or mapping experience, or work with other placement-sensitive systems where topology materially affects communication.
  • Experience with AI or high-performance computing communication stacks such as NCCL, RCCL, MPI, SHMEM, or proprietary collective libraries.
  • Experience with RoCE, InfiniBand, PCIe, CXL, or other relevant scale-out and I/O technologies.
  • Experience with workload-driven modeling, traffic simulation, emulation, or pre-silicon and post-silicon correlation.
  • Working awareness of SerDes, packaging, retimers, cabling, optics, and reach constraints.

About the Company

Cerebras

AI accelerator hardware replacing GPUs

Cerebras Systems creates AI acceleration hardware and software. Its CS-2 system is designed to replace traditional GPU clusters for AI workloads, speeding up training and inference while simplifying the setup by eliminating the need for parallel programming, distributed training, and cluster management. The product works as a single, large processor-based accelerator with accompanying software and cloud services to run AI models efficiently, reducing latency and time to results. Compared with competitors, Cerebras differentiates itself with the largest processor in the industry and an integrated hardware-software stack that aims to streamline AI workflows rather than relying on multi-GPU clusters. The company's goal is to help research labs, healthcare, finance, and other industries achieve faster, more cost-effective AI development and deployment by offering a turnkey high-performance AI compute solution.

Company size
501-1,000
Company stage
IPO
Headquarters
Sunnyvale, CA
Founded
2016

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