CScale

Optical interconnects for large-scale AI infrastructure

Senior Design Verification Engineer

Hardware Validation & TestingConfirmed live in the last 24 hours

Full-timeBengaluru, Karnataka, IndiaNo salary listedIn-person

About the Job

Requirements

A B.E., B.Tech, M.E., or M.Tech in Electrical, Electronics, or Computer Engineering is required.
Five to seven years of hands-on design verification development and integration experience in SoC, networking, or interconnect logic is required.
Proficiency in SystemVerilog and UVM coding for verification, with knowledge of C, is required.
Experience with ARM or RISC-V CPU subsystems is required.
A solid understanding of connectivity and interconnect protocols such as AMBA (AXI/AHB/APB) is required.
Knowledge of clock/reset architectures, FIFOs, clock-domain crossing, and low-power verification techniques is required.
Hands-on experience with simulation tools such as VCS or Questa is required.
Strong knowledge of Unified Power Format, level-shifter implementation, and power-management strategies for low-power design is required.
Experience with Git flow is required.

Responsibilities

Take ownership of test-bench development using UVM for subsystem and SoC.
Translate test-bench architecture specifications into detailed design verification tasks and build verification environments from scratch.
Develop test-bench components including agents, scoreboards for data-integrity checks, pass/fail criteria, protocol assertions, and functional-coverage points.
Set up UVM register-model generation using register-description files and industry-standard automation tools such as Autogen.
Automate generation of C-based register-programming APIs from register-description files through scripting.
Perform complete address-map and register verification using UVM Register methodology.
Verify features through standalone test cases, concurrent traffic, use-case scenarios, and corner cases.
Debug regression failures, perform root-cause analysis, and collaborate with designers to resolve issues.
Perform power-aware verification across voltage corners, validating power and sub-power domains and retention strategies.
Set up and execute gate-level simulations, including a dedicated test suite covering system boot and main data-path functionality.

Desired Qualifications

Familiarity with PCIe or Ethernet is a plus.

CScale is building the interconnect for gigawatt-scale AI. As AI scale-up moves toward deployments spanning thousands of accelerators and dozens of racks, the network needs to deliver high bandwidth, predictable low latency, and continuous communication. CScale is building integrated optical interconnect designed for this new scale, enabling accelerators to work together like a single, much larger computer. But at this scale, performance is only part of the challenge. Optical failures are inevitable, and the system needs to keep running. CScale is designing the interconnect for continuity.Lasers will fail. Compute shouldn’t.The ambition is simple:Build AI interconnect you can take for granted.CScale came out of stealth in September 2026 with $145 million in Series C funding, bringing total funding to $188 million.

We are seeking a Senior Design Verification Engineer (5–7 years of experience) to join our Data Center Connectivity DV team. This role is ideal for engineers passionate about building verification environments from the ground up, performing functional and power-aware simulations, and integrating VIPs for standard protocols such as MAC, PHY, and AXI. The position involves CPUSS integration, verification of cutting-edge technologies.

Key Responsibilities

Take ownership oftest-bench development usingUVM for Subsystem and SoC.
Translate test bench architecture specifications into detailed DV tasks and build verification environments from scratch.
Develop key test bench components including agents, scoreboards for data integrity checks, pass/fail criteria, protocol assertions, and functional coverage points
Set up UVM register model generation using register description files and industry-standard automation tools (e.g.,Autogen).
Automate C-based register programming API generation from register description files through scripting.
Perform complete address map and register verification using UVM Register methodology.
Verify all features comprehensively, including standalone test cases, concurrent traffic, use-case scenarios, and corner cases.
Debug regression failures, perform root cause analysis, and collaborate closely with designers to resolve issues
Perform comprehensive power-aware verification across all voltage corners, validating power and sub-power domains along with retention strategies.
Set up and execute gate-level simulations, including a dedicated test suite for GLS that covers system boot and main data-path functionality

Required Skills and Experience

Education: B.E./B.Tech/M.E./M.Tech in Electrical, Electronics, or Computer Engineering.
Experience: 5–7 years of strong hands-on DV development and integration experience in SoC, networking, or interconnect logic.
Proficiency in System Verilog and UVM coding for verification. Knowledge of C language.
Experience with ARM or RISC-V CPU subsystems.
Solid understanding of connectivity and interconnect protocols such as AMBA (AXI/AHB/APB); familiarity with PCIe or Ethernet is a plus.
Knowledge of clock/reset architectures, FIFOs, CDC, and low-power verification techniques.
Strong debugging and problem-solving skills; experience with Git flow.
Hands-on experience with simulation tools (e.g.,VCS, Questa).
Strong knowledge of UPF (Unified Power Format), level shifter implementation, and power management strategies for low-power design.

Why This Role

Work on next-gen data center connectivity.
Gain deep exposure toDV architecture,UVM based TB development, E2E SoC development cycle and post-silicon bring-up.
Be part of a highly technical team that values innovation, ownership, and learning.
Competitive compensation, technical growth, and exposure to cutting-edge design challenges.

About the Company

CScale

Optical interconnects for large-scale AI infrastructure

CScale builds optical interconnects for large-scale AI computing. Its integrated light engines power gigawatt-scale AI facilities by containing optical failures and keeping compute running across thousands of closely connected accelerators. The hardware provides high-bandwidth, ultra-low-latency optical links to connect accelerators across racks, making data movement between chips dependable for continuous AI workloads. Unlike many data-center components that rely on electronic signaling, CScale focuses on silicon photonics and photonic hardware to deliver scalable, reliable communication at scale. Founded in 2023 in Palo Alto, the company exited stealth in 2026 and has investors including NVIDIA and Intel Capital. Its goal is to enable uninterrupted AI training and inference across large AI infrastructure by delivering dependable optical interconnects that scale as data-center needs grow.

Company size: 51-200
Company stage: Series C
Total funding: $145M
Headquarters: Palo Alto, CA
Founded: 2023

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