Senior Engineer Hig Hbm Layout

For more than 45 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life.

We are hiring a Layout Engineer for Micron Technology’s HBM Team in Hyderabad, India. In this role, you will contribute to advanced applications including artificial intelligence and high-performance computing solutions with High Bandwidth Memory. You will coordinate with peer groups across Micron's worldwide locations on multiple projects, providing an exceptional chance for career development!

Role and Responsibilities

• Build and develop critical analog, mixed-signal, custom digital blocks, and provide full chip level integration support.
• Build and tapeout PWF Reticles.
• Collaborate with the Scribe Build team to implement and review Advanced Packaging requirements.
• Engage in TSV build with HIG-HBM DTPCO teams, ensuring flawless electrical, thermal, and mechanical performance.
• Exhibit a highly motivated, diligent, meticulous, and methodical approach in IC layout development.
• Perform layout verification like LVS/DRC/Antenna checks, quality control, and documentation.
• Ensure timely delivery of block-level layouts with outstanding quality.
• Demonstrate leadership in planning, area/time estimation, scheduling, delegation, and execution to meet project schedules and achievements in a multi-project environment.
• Guide less experienced team members in their completion of sub-block-level layouts and review their work.
• Contribute to effective project management.
• Communicate effectively with global engineering teams to ensure the success of layout projects.

Qualification/Requirements

• 6+ years' experience in analog/custom layout development in advanced CMOS processes across various technology nodes (Planar, FinFET).
• Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS.
• Hands-on experience in crafting layouts of critical blocks such as Temperature sensors, PLL, ADC, DAC, LDO, Bandgap, Reference Generators, Charge Pumps, Current Mirrors, Comparators, Differential Amplifiers, etc.
• Strong understanding of analog layout fundamentals (e.g., matching, electromigration, latch-up, coupling, crosstalk, IR-drop, active and passive parasitic devices).
• Ability to understand and implement build constraints to develop high-quality layouts.
• Knowledge of build hierarchy and various memory build architectures.
• Excellent problem-solving skills in physical verification of custom layouts.
• Multiple tape-out support experience is advantageous.
• Capability in managing multiple layout projects with strict quality checks at all development stages.
• Excellent verbal and written communication skills.

Education

BE or MTech in Electronic/VLSI Engineering

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran, or disability status.