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Synopsys

EDA software for chip design

Applications Engineering – Senior Engineer

Implementation & Technical Account ManagementUpdated on Nov 13
Full-timeIsraelNo salary listed

About the Job

Requirements

  • Solid working knowledge of Static Timing Analysis and ECO closure, including explaining timing concepts, constraints, and methodologies to design teams.
  • Direct experience with at least two chip tapeouts at 16nm or below, with responsibility for timing closure or ECO implementation.
  • Hands-on proficiency with Synopsys PrimeTime, including running Static Timing Analysis, analyzing timing reports, and debugging violations.
  • Understanding of timing corners, process variation (OCV, AOCV, POCV), and signal-integrity effects such as crosstalk and IR drop.
  • Experience with ECO flows using PTECO or PrimeClosure, including gate sizing, buffer insertion, and logic restructuring.
  • BSEE or equivalent with 5+ years of relevant experience, or MSEE with 3+ years of relevant experience, focused on digital design, timing analysis, or applications engineering.

Responsibilities

  • Drive adoption of PrimeTime and PrimeClosure across customer accounts in pre-sale evaluations and post-sale deployment, working with design teams to integrate the tools into their flows.
  • Run competitive benchmarks against other Static Timing Analysis tools and document performance, accuracy, and capacity in customer design contexts.
  • Deliver hands-on training sessions and technical workshops to customer engineering teams on timing-closure methodology, ECO flows, and advanced PrimeTime features.
  • Partner with R&D and product marketing to translate customer pain points into feature requests, providing use cases and technical requirements that inform the product roadmap.
  • Troubleshoot complex timing issues in customer designs, including issues related to timing corners, process variation, crosstalk, and signal integrity.
  • Present technical solutions and methodology recommendations to design engineers and engineering management, tailoring the presentation to each audience.
  • Build and maintain technical relationships with key customers and advise them on timing-closure challenges.

Desired Qualifications

  • Familiarity with scripting in TCL or Python to automate analysis tasks and customize flows.

About the Company

Synopsys

EDA software for chip design

Synopsys provides software tools and services for electronic design automation (EDA), helping engineers design, simulate, verify, and optimize semiconductor chips and systems. Its products cover the full design flow, including RTL-to-gating synthesis, place-and-route, timing analysis, verification, and silicon validation, as well as software integrity solutions and hardware-assisted verification. Engineers use these tools to model, simulate, and validate complex chip designs before manufacturing, reducing bugs and improving performance. Compared with many competitors, Synopsys differentiates itself through its broad, end-to-end design toolchain, large ecosystem of IP and integration with simulation and modeling capabilities gained from its 2025 merger with ANSYS, and its global scale and support. The company aims to help designers push the boundaries of chip and system performance, accelerate time-to-market, and enable silicon-to-systems design across a wide range of industries.

Company size
10,001+
Company stage
IPO
Headquarters
Sunnyvale, CA
Founded
1986

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