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Analogue Insight

Analog/mixed-signal IP and SoC design

Graduate Analog Design Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeRemote in UKNo salary listed

About the Job

Requirements

  • A Master of Science or Ph.D. in Electrical/Electronic Engineering or a related field, focused on analog/mixed-signal circuit design; recent graduates and candidates graduating within the next six months are welcome.
  • Zero to two years of industry experience, including internships, placements, or research projects.
  • A strong grasp of analog fundamentals, including CMOS device physics, small-signal analysis, feedback and stability, noise, and mismatch.
  • Hands-on circuit design and simulation experience with Cadence Virtuoso/Spectre or similar tools through coursework, a thesis, or internship projects.
  • Understanding of at least one of data converters (ADC/DAC), PLLs/clocking, or high-speed TX/RX circuits.
  • Clear, structured communication in professional English, including the ability to explain complex results concisely.
  • A collaborative and feedback-oriented mindset, openness to learning from design reviews, strong ownership, reliability, and follow-through.
  • Curiosity, self-motivation, eagerness to learn and explore new tools or methods, integrity, and professionalism in representing the company and handling sensitive information.

Responsibilities

  • Design and optimise sub-blocks of ADC, DAC, RX, TX, and PLL circuits, such as amplifiers, comparators, bias circuits, references, and clock buffers, under the guidance of senior designers.
  • Run transistor-level simulations (DC, AC, transient, noise, Monte Carlo, and PVT corners) and mixed-signal verification using Cadence, AMS, and SystemVerilog to confirm robust performance across operating conditions.
  • Learn and apply design techniques to improve gain, bandwidth, linearity, noise, jitter, power consumption, and speed.
  • Work closely with layout engineers to communicate matching, symmetry, and parasitic-sensitive nets, and run post-layout extracted simulations to close the design.
  • Build behavioural models, such as Verilog-A, and scripts, such as Python, SKILL, or OCEAN, to speed up simulation, analysis, and design-check flows.
  • Help prepare test plans and support lab characterisation and debug of silicon as projects progress.
  • Document designs, simulation results, and design-review material clearly to support knowledge sharing within the team.
  • Keep learning about advances in high-speed SerDes, data converters, and chiplet interfaces such as UCIe.

Desired Qualifications

  • Thesis, research, or internship work on FinFET or other advanced-node technologies.
  • Completed tape-out and/or lab measurement experience.
  • Familiarity with Verilog/SystemVerilog, Verilog-A, or AMS modelling.
  • Scripting experience with Python, MATLAB, SKILL, or shell, and comfort in a Linux environment.
  • Publications or conference contributions in circuits, such as ISSCC, VLSI, CICC, or ESSCIRC.

About the Company

Analogue Insight

Analog/mixed-signal IP and SoC design

Analogue Insight provides analog and mixed-signal IP, custom silicon, and SoC/chiplet programs for semiconductor firms. It delivers end-to-end design services—from architecture and IP development to physical design and security IP—and also develops and licenses IP blocks such as die-to-die connectivity (UCIe), SerDes, DDR, USB, and Ethernet. The company stands out by being profitable and self-funded since its 2024 founding, operating through a UK-based IP group with a new US division focused on high-assurance security IP, led by veterans in the field. Its goal is to help customers design, validate, and deploy sophisticated analog/mixed-signal IP and chiplets while expanding security IP licensing globally.

Company size
11-50
Company stage
Not listed
Total funding
Not listed
Headquarters
London, United Kingdom
Founded
2024

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