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Micron Technology

Makes memory and storage chips for AI and PCs

Lead Principal Engineer - Layout Design

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeMexicoNo salary listedIn-person

About the Job

Requirements

  • At least 10 years of experience in the semiconductor industry.
  • A bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience.
  • Strong understanding of CMOS devices and layout-dependent effects.
  • Hands-on experience with custom integrated-circuit layout and physical verification tools.
  • Comprehensive understanding of reliability checks and layout constraints.
  • Experience leading technical execution and delivering tapeouts.
  • Proficiency in scripting and automation to improve layout efficiency.

Responsibilities

  • Lead the layout build and physical realization of new memory products.
  • Interpret device and circuit specifications to implement custom layout solutions meeting power, performance, area, and reliability targets.
  • Develop hierarchical layouts for analog, digital, and memory-array-related circuitry using industry-standard electronic design automation tools.
  • Build block and top-level floorplans optimizing placement, routing resources, signal integrity, power delivery, and manufacturability.
  • Optimize layout for die size and area efficiency, matching, coupling and noise, and timing.
  • Produce layout collateral and documentation for cross-team integration.
  • Run and debug physical verification flows and ensure closure using industry tools.
  • Perform parasitic extraction and work with circuit designers to assess impact on timing, power, noise, and functionality.
  • Resolve layout issues related to signal integrity, coupling and crosstalk, antenna effects, and power integrity.
  • Drive standard physical build practices and maintain layout documentation.
  • Participate in continuing education on advanced nodes and industry trends.
  • Solicit feedback from various groups to ensure layout quality and tool-flow robustness.
  • Innovate for future memory generations through layout-centric optimizations and improved methodologies.
  • Lead resource planning, priorities, and tapeout schedules across multiple blocks.
  • Serve as the contact for layout implementation, physical verification, parasitic extraction/signoff, and integration issues.
  • Track closure of achievements and coordinate engineering change order execution to meet tapeout landmarks.
  • Communicate implementation status to technical leadership and management.

Desired Qualifications

  • A master's degree or PhD in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience in lieu of either degree.
  • In-depth knowledge of advanced-node layout considerations and memory/storage technology trends.

About the Company

Micron Technology

Makes memory and storage chips for AI and PCs

Micron Technology designs and manufactures memory and storage chips, mainly DRAM and NAND flash, used in data centers, PCs, phones, cars and industrial equipment. It is one of only three companies that make HBM, the stacked high-bandwidth memory placed beside processors in AI servers, and it is the largest memory chipmaker based in the United States. Unlike chip designers that outsource production, Micron runs its own fabs and assembly sites in the United States and across Asia. It earns money by selling chips, memory modules and solid-state drives to cloud providers, device makers and distributors. Micron was founded in 1978 and is headquartered in Boise, Idaho.

Company size
10,001+
Company stage
IPO
Headquarters
Boise, ID
Founded
1978

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