Physical Design Engineer Intern

Physical Design Engineer Intern (DM)

Astera Labs · San Jose, CA · Internship · On-site

About Astera Labs

Astera Labs builds connectivity solutions that help power modern AI infrastructure. Our silicon teams develop complex digital products where power, performance, area, timing, physical implementation, and manufacturability must come together reliably.

The opportunity

Join the Physical Design team and gain hands-on experience taking a digital design from RTL handoff through physical implementation and signoff. You’ll learn how physical design methodology and flow infrastructure turn design intent into an efficient, manufacturable layout while helping improve repeatability, productivity, and design quality.

This internship is designed for someone who enjoys both engineering fundamentals and practical problem-solving: running a flow, reading timing and QoR reports, investigating a broken stage, adjusting constraints or configuration, and measuring the effect of an iteration. You’ll work with experienced physical design, CAD, front-end, STA, EMIR, and physical-verification engineers on a meaningful project.

What you’ll do

• Learn the physical design flow, development environment, project structure, tools, and methodology needed to contribute effectively.

• Run an assigned block through the RTL-to-signoff flow, including synthesis, floorplanning, power planning, placement, clock-tree synthesis, routing, optimization, timing closure, and signoff.

• Review physical design inputs such as RTL or netlists, SDC constraints, technology files, libraries, LEF/tech files, QRC data, and PDK-related inputs.

• Analyze timing, area, utilization, congestion, clock skew, insertion delay, transition, DRC, LVS, EMIR, and other quality-of-result reports.

• Help identify and resolve flow, implementation, timing, congestion, physical-verification, or infrastructure issues with guidance from experienced engineers.

• Support PPA exploration by running controlled experiments, comparing configurations, tracking results, and documenting the tradeoffs between power, performance, and area.

• Work with physical-design flow configuration, scripts, experiment definitions, reports, logs, and reproducible work areas.

• Contribute to CAD and flow infrastructure improvements such as report generation, run orchestration, validation checks, log mining, root-cause analysis, or handoff packaging.

• Use tools and flows such as Fusion, Innovus, PrimeTime, Calibre, Voltus, or related EDA environments under engineering guidance.

• Collaborate with front-end design, synthesis, STA, EMIR, physical verification, and other teams on inputs, handoffs, signoff criteria, and issue resolution.

• Participate in design reviews, code or flow reviews, technical discussions, issue tracking, documentation, and project planning.

• Deliver assigned physical-design work in a reproducible, well-documented state and present your project, results, and key learnings at the end of the internship.

What you bring

• Coursework, projects, research, or hands-on experience in electrical engineering, computer engineering, computer science, VLSI, or a related field.

• Foundational understanding of digital logic, RTL, CMOS/ASIC design, computer architecture, timing, or semiconductor manufacturing.

• Interest in the physical implementation of digital designs and how layout decisions affect power, performance, area, timing, congestion, and manufacturability.

• Experience with Linux, command-line tools, source control, or scripting through coursework, projects, research, or prior experience.

• A methodical approach to debugging: understand the inputs, reproduce the issue, inspect reports and logs, test a focused change, and evaluate the result.

• Ability to learn unfamiliar tools and technical concepts, ask focused questions, communicate progress and blockers, and follow through on commitments.

• Self-motivation, professionalism, ownership, and a collaborative mindset.

Helpful experience

• ASIC physical design, synthesis, floorplanning, placement, CTS, routing, timing closure, physical verification, or EMIR.

• Static timing analysis, multi-mode/multi-corner concepts, clock constraints, setup/hold analysis, slack, skew, or useful skew.

• Power planning, standard-cell placement, macro placement, congestion analysis, DRC/LVS, antenna checks, or power-integrity analysis.

• Tcl, Python, Bash, YAML, or other scripting and configuration languages used to automate engineering workflows.

• Synopsys Fusion Compiler, Cadence Innovus, PrimeTime, Calibre, Voltus, or comparable EDA tools.

• Git, Bitbucket, P4, Slurm, Snakemake, or other tools used for reproducible, compute-intensive engineering flows.

• Experience comparing QoR across experiments, generating reports, visualizing trends, or debugging flow infrastructure.

Internship experience and compensation

This is a paid, hourly U.S. internship. The applicable hourly rate is determined as part of the offer process and specified in the offer letter, depending on education level ranges form $35/hour to $55/hour. U.S. interns currently receive a $500-per-week housing/relocation stipend for the duration of the internship. Interns participate in Early Career programming, including technical and professional-development sessions, community events, and an end-of-program project presentation.

Equal opportunity

Astera Labs is committed to providing equal employment opportunities to all applicants and employees. We value diverse perspectives and consider qualified candidates without regard to legally protected characteristics.