ASIC Design – Principal Engineer

Job Responsibilities:

• As a member of the ASIC Design team, you will work closely with the architecture team and define and document micro-architecture on next generation designs. 
• Responsible for the logic design/RTL entry that meets the power, performance, area targets. 
• Collaborate closely with design verification and emulation teams to confirm that test plans meet architecture and design intent, debug complex test scenarios and coverage closure
• Work closely with the physical design team on timing closure and area optimization 
• Work with the design for test team to integrate DFT logic
• Work independently, communicate effectively and collaborate with cross functional teams 

Requirements:

• BE or MS in EE, CE, CS 
• 5+ years of related technical engineering experience.
• 5+ years of industry experience in logic design on complex ASICs
• Experience with SystemVerilog for logic design
• Understanding of fundamental principles of logic design, clock domain crossing, synthesis and timing closure
• Proficient communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
• Able to thrive or lead in a fast-paced startup environment.

Preferred:

• 12+ years of relevant industry experience with a proven track record of successful tapeouts 
• Scripting proficiency using Python, Perl etc. 
• Experience with front end design tools like LINT, CDC, RDC
• Exposure to silicon bring-up 
• Analyzing timing, area, power reports and ability to drive design fixes 
• Knowledge of verification principles and coverage and ability to debug complex test cases
• Basic understanding of formal verification 
• Past work experience on high performance, low latency networking ASICs is a big plus 
• Growth mindset and enthusiasm to learn and grow in a fast paced environment