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Astera Labs

Designs chips that connect data center systems

Product Technical Chip Lead Senior Director

Engineering LeadershipConfirmed live in the last 24 hours
Full-time

About the Job

Requirements

  • A bachelor's degree in Electrical Engineering, Computer Engineering, or a related field is required.
  • At least 15 years of experience across architecture, silicon design, validation, systems, or related domains is required.
  • A proven track record developing large-scale chips of 300 mm² or more through successful tapeout is required.
  • Hands-on experience with 2.5D and 3D advanced packaging technologies and chiplet-based architectures is required.
  • Strong understanding of RTL design, design verification, design for test (DFT), and physical design flows is required.
  • Experience with high-speed serial interfaces such as PCIe, Ethernet, or switching architectures is required.
  • Demonstrated executive leadership of cross-functional technical programs with end-to-end product cycle ownership is required.
  • Strong communication and executive presence to influence at all levels of the organization are required.

Responsibilities

  • Own the full technical lifecycle of the product line, including architecture assumptions, design integration, validation strategy, readiness, and customer enablement.
  • Drive chip development execution from RTL to GDSII and ensure architecture, implementation, and tapeout milestones are met.
  • Lead development of large-scale chips (300–400 mm²) using 2.5D/3D advanced packaging technologies and chiplet-based architectures.
  • Translate product requirements into clear priorities, tradeoffs, and execution paths to reduce ambiguity.
  • Own chip tapeout and chip signoff, with full responsibility for chip quality.
  • Anticipate challenges and drive alignment across engineering functions, ensuring risks, dependencies, and decisions are surfaced and resolved early.
  • Partner with design verification teams to define coverage goals, regression strategies, and sign-off criteria.
  • Collaborate with DFT teams on test architecture, scan insertion, BIST, and manufacturing test strategies.
  • Work closely with physical design teams on timing closure, power optimization, and backend execution.
  • Establish and reinforce scalable processes, documentation, and handoffs that support company growth.
  • Provide structured, data-driven decision-making and maintain a consistent operational cadence across the product line.
  • Transform conflicts to foster a culture of ownership, mentor and elevate teams, and strengthen technical judgment, accountability, and cross-functional collaboration.
  • Model calm leadership, particularly in high-stakes or ambiguous situations.
  • Shape engineering culture and talent strategy to support the company's growth.

Desired Qualifications

  • A master's degree in Electrical Engineering or Computer Engineering is preferred.
  • Experience with UALink, UCIe, PCIe Gen5/Gen6/Gen7, or Ethernet switching architectures is preferred.
  • Experience with advanced process nodes (7 nm, 5 nm, or below) is preferred.
  • A background in power management, clocking architectures, or high-speed analog integration is preferred.
  • Experience operating in fast-growing startup or hyperscale environments is preferred.

About the Company

Astera Labs

Designs chips that connect data center systems

Astera Labs designs chips and hardware modules that move data between processors, memory and accelerators in data centers. Its customers include cloud providers, chip vendors and equipment makers building servers and large computing clusters for AI and other workloads. Retimers restore signal quality, switches connect devices and memory controllers expand the memory available to computing systems, while COSMOS software monitors and manages these links. The company sells its products directly and through distributors, using outside manufacturers to fabricate and assemble its hardware. Astera Labs was founded in 2017 and is headquartered in San Jose, California.

Company size
501-1,000
Company stage
IPO
Headquarters
San Jose, CA
Founded
2017

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