Physical Design Engineer - Power Integrity

The Silicon Platform Team acts as the core R&D middleware group for chip development within the company. The team covers the full spectrum of the chip design flow, including Logic Synthesis, Design for Testability (DFT), Backend Design, Physical and STA (Static Timing Analysis) Signoff, as well as Power Integrity, IR drop, and Electromagnetic Compatibility (Power/IR/EM). The team also oversees tape-out, mass production, packaging, testing, and board-level verification. They collaborate closely with front-end chip teams across business units to drive R&D progress and mass production deployment for chips. Responsibilities - Own Power Integrity (PI) signoff for advanced-node ASIC/SoC designs including advanced package, covering Static IR Drop, Dynamic IR Drop, Electromigration (EM), Power Grid Analysis, In-rush Current, Power-up/Power-down analysis, Load Step/Transient analysis, and Package/Board/PDN co-analysis. - Lead full-chip and block-level power integrity analysis from early design through tapeout, including power delivery network modeling, power-domain analysis, vectorless and vector-based simulation, and PI signoff methodology and closure. - Drive early-stage PI methodology and flow bring-up, especially for new process nodes, early PDKs, immature technology files, and new power architectures. - Analyze and debug complex PI results, including static/dynamic IR hotspots, EM violations, current spikes, power-grid connectivity issues, power switch behavior, package-induced voltage noise, decap effectiveness, LDO/VRM response, and load-step/power-up transient behavior. - Work closely with Physical Design, RTL/Design, Power Architecture, Package, Analog/PMIC, Library, Foundry, and EDA teams to resolve PI issues and achieve signoff closure. - Act as the technical interface with Foundry and EDA vendors on PI-related issues, including technology/rule interpretation, EM/IR rule requirements, metal stack and resistance assumptions, package model correlation, and tool discrepancy resolution. - Develop and optimize PI methodologies for advanced-node designs, including vector-based/vectorless analysis, activity generation and coverage, static/dynamic IR analysis, EM analysis, power-up/ramp-up analysis, load-step analysis, power-switch analysis, and package-aware analysis. - Establish PI signoff criteria, methodology, and best practices, and provide technical guidance to peer engineers. Minimum Qualification(s) - BS degree in Electrical Engineering, Computer Engineering, or equivalent practical experience. - 5+ years of experience in power integrity analysis for ASIC/SoC designs. - Hands-on experience with industry-standard PI tools (e.g., Ansys RedHawk-SC, Synopsys PT-PX, Cadence Voltus). - Experience with static and dynamic IR drop analysis, EM analysis, and power grid analysis. - Experience with PI signoff flow from early design through tapeout. Preferred Qualification(s) - Experience with 7nm/5nm/3nm/2nm or other advanced nodes. - Experience with advanced package PI co-analysis (package/board/PDN). - Experience with early-stage PI methodology bring-up for new process nodes. - Experience working with Foundry and EDA vendors on PI rule interpretation and tool correlation.