A

AMD

Designs chips for computers and AI systems

Principal Competitive CPU Microarchitecture & Platform Performance Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeAustin, TX, USANo salary listedIn-person

About the Job

Requirements

  • Deep hands-on experience in CPU microarchitecture, silicon performance, system architecture, or performance modeling.
  • Strong knowledge of out-of-order pipelines, branch prediction, fetch and decode, execution back ends, and simultaneous multithreading behavior.
  • Expertise in cache, translation lookaside buffer (TLB), coherence, prefetching, memory controllers, non-uniform memory access (NUMA), bandwidth, latency, and capacity scaling.
  • Experience with hardware performance counters, profiling tools, microbenchmarks, system telemetry, and bottleneck analysis.
  • Strong quantitative and scripting or data-analysis skills used in performance investigations.
  • Ability to reason from incomplete information, make assumptions explicit, and show which unknowns can change the conclusion.
  • Clear technical writing and visualization skills, with a commitment to configuration control, peer review, and reproducibility.
  • Bachelor's or Master's degree in electrical or computer engineering.

Responsibilities

  • Develop comparative models of CPU front ends, execution resources, branch behavior, cache and TLB hierarchies, coherence, memory subsystems, and multi-socket or NUMA behavior.
  • Model platform constraints and advantages, including memory bandwidth and capacity, DDR or HBM attachment where relevant, PCIe, CXL, networking, storage paths, power limits, and thermals.
  • Translate incomplete roadmap disclosures into explicit assumptions with confidence levels, alternate cases, and sensitivity ranges.
  • Use measured silicon, performance counters, and platform telemetry to calibrate models and identify failing assumptions.
  • Perform bottleneck decomposition to explain why a workload favors AMD or a competitor and which architectural mechanism is responsible.
  • Work with workload engineers to create microbenchmarks and kernels that isolate high-value architectural effects.
  • Evaluate ISA and acceleration features in the context of real application uplift rather than theoretical peak capability.
  • Quantify performance-per-watt, platform power, and rack-density implications when architectural choices change system behavior.
  • Maintain version-controlled assumptions, sources, revisions, and uncertainty so forecasts can be peer reviewed and reproduced.
  • Create architecture diagrams, technical narratives, and executive-ready content that clearly show causes, risks, and areas of AMD advantage.

Desired Qualifications

  • Pre-silicon performance modeling, architecture exploration, or simulation experience.
  • Hands-on analysis of more than one server CPU architecture or instruction set architecture (ISA).
  • Experience with memory-intensive workloads, virtualization, high-performance computing (HPC), analytics, or CPU-side artificial intelligence workloads.
  • Familiarity with power modeling, thermals, platform firmware, and frequency or power-management behavior.
  • Experience evaluating vendor disclosures, patents, conference presentations, or public technical materials under clean-room rules.

About the Company

AMD

Designs chips for computers and AI systems

AMD designs processors, graphics chips and AI accelerators for computer makers, cloud operators and businesses that build electronic devices. Its Ryzen processors power personal computers, while EPYC processors handle work in data centers and Radeon chips render graphics. Instinct accelerators run AI models, paired with software that developers use to train models and put them into production. AMD sells chips and related computing systems through equipment makers, distributors and retail channels, and contracts with outside foundries to fabricate its semiconductor designs. It was founded in 1969 and has its headquarters in Santa Clara, California.

Company size
10,001+
Company stage
IPO
Headquarters
Santa Clara, CA
Founded
1969

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