Volantis Semiconductor

Designs photonic AI compute hardware

Architect-Subsystem

Silicon & ASIC DesignConfirmed live in the last 24 hours

Full-timeNo salary listedHybrid

About the Job

Requirements

Hands-on experience owning and delivering the architecture of a block that was part of a larger chip or system.
Understanding and hands-on experience in the design of AI accelerators.
Experience working with microarchitects in the implementation and verification of a block.

Responsibilities

Own key blocks on the A-0 and A-1 systems, with responsibility for an entire sub-block.
Understand how the sub-block fits into the entire system and work with other architects and architecture leaders to integrate it into the broader system.

Desired Qualifications

Experience with the physical design process of a block previously owned.
Experience with large-die-area chips.
Experience with multi-die and multi-package chips and systems.

What We’re Looking For:

We’re looking for architects to own key blocks on the A-0 and A-1 systems. This is a role with ownership of an entire sub-block, and you will need to understand how it fits into the entire system and work with other architects and architecture leaders to integrate it into the broader system.

Ideal Background:

Hands-on experience in owning and delivering the architecture of a block that was part of a larger chip/system.
Understanding and hands-on experience in the design of AI accelerators
Experience working with microarchitects in the implementation and verification of said block

Nice to Have:

Experience with the physical design process of the block you owned
Experience with large die area chips
Experience with multi-die and multi-package chips and systems

About the Company

Volantis Semiconductor

Designs photonic AI compute hardware

Volantis Semiconductor designs photonic computing hardware for AI workloads, centered on the Volantis Photonic Motherboard. Its technology directly modulates low-cost VCSELs and densely parallel optical waveguides directly on the chip to replace electrical interconnects, enabling a chip-scale package with massive bandwidth and energy efficiency. This approach differs from traditional silicon photonics by wafer-scale integration and laser-based optics, focusing on scalable interconnect bandwidth and compute efficiency rather than simply adding more silicon cores. The company aims to deliver faster, cheaper AI compute with reduced energy use, with pre-orders expected in early 2026 as it engages early customers.

Company size: 11-50
Company stage: Series A
Total funding: $97M
Headquarters: San Mateo, CA
Founded: 2022

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