Board Design Manager

• Define system specifications, block diagrams, power trees, clock distribution topologies, and component selection for server-class silicon validation platforms and characterization fixtures.
  
• Drive schematic capture and guided physical layout for high-density interconnect, ultra-high-layer-count (24+ layers) printed circuit boards utilizing advanced dielectric materials using Cadence Allegro, Concept, and OrCAD.
• Partner with Signal Integrity and Power Integrity teams to implement decoupling strategies, multi-phase voltage regulator module designs capable of delivering high-current rails (>500 amperes to 1000+ amperes), and impedance-controlled high-speed routing.
• Direct post-silicon board bring-up in the laboratory using high-speed oscilloscopes, logic analyzers, and thermal imaging; mentored team members and established organization-wide hardware design guidelines.
• Enforce strict Design for Manufacturing, Design for Assembly, and Design for Test guidelines; partnered with printed circuit board fabricators and electronics manufacturing service assembly houses to resolve technical issues and optimize yield.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience
• 10 years of experience in high-speed, multi-layer board-level hardware design.
• 5 years of experience managing teams.
• Experience designing and routing high-speed digital interfaces (e.g., PCIe Gen6, DDR5/LPDDR6, USB4, I3C, SPI, high-speed SerDes) and clock distribution networks.
• Experience in schematic capture and PCB layout tools (specifically Cadence Allegro Design Authoring/Concept HDL and Allegro PCB Editor).
• Experience designing multi-phase point-of-load (PoL) voltage regulators, high-efficiency DC-DC converters, power sequencing, and high-transient power delivery systems.

Preferred qualifications:

• Master's degree in Electrical Engineering or Computer Engineering with a focus on Hardware Systems, Power Electronics, or High-Speed Circuit Design.
• 12 years of experience designing Reference Validation Platforms (RVPs), ATE characterization boards, or server motherboards for enterprise CPUs or AI/ML accelerators (TPUs/GPUs).
• Experience designing ultra-high-current power delivery networks (>1000A) with advanced digital multi-phase PWM controllers (PMBus/AVS).
• Experience leading multi-disciplinary engineering projects, driving ODM/EMS vendors, and mentoring junior/mid-level hardware engineers.
• Deep knowledge of HDI, micro-vias, rigid-flex, low-loss laminate selection, and advanced manufacturing capabilities at PCB fabrication vendors.

Google's mission is to organize the world's information and make it universally accessible and useful. As a Staff Board Design Engineer within the Silicon Systems and Engineering team, you will serve as the lead technical authority driving the architecture, schematic design, and complex layout of mission-critical printed circuit board platforms that power Google’s next-generation custom silicon—including Google Cloud Axion central processing units and Tensor Processing Units.

In this role, you will lead the end-to-end hardware development of advanced Reference Validation Platforms, silicon characterization boards, and high-density test fixtures.

You will manage bleeding-edge electrical, thermal, and mechanical tests—from designing high-current multi-phase power delivery networks to routing multi-gigabit high-speed serial links across ultra-high-layer-count substrates.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

• Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience
• 10 years of experience in high-speed, multi-layer board-level hardware design.
• 5 years of experience managing teams.
• Experience designing and routing high-speed digital interfaces (e.g., PCIe Gen6, DDR5/LPDDR6, USB4, I3C, SPI, high-speed SerDes) and clock distribution networks.
• Experience in schematic capture and PCB layout tools (specifically Cadence Allegro Design Authoring/Concept HDL and Allegro PCB Editor).
• Experience designing multi-phase point-of-load (PoL) voltage regulators, high-efficiency DC-DC converters, power sequencing, and high-transient power delivery systems.