Google

Runs Search and YouTube and builds Gemini AI

ASIC Formal Verification Engineer - TPU Compute

Hardware Validation & TestingConfirmed live in the last 24 hours

Full-timeSunnyvale, CA, USAIn-person

About the Job

Requirements

A bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
At least 8 years of experience in silicon development or ASIC/SoC design.
Experience with SystemVerilog Assertions (SVA) and formal verification methods.
A master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture is preferred.
At least 10 years of experience with industry-standard tools, languages, and methodologies relevant to developing silicon-based integrated circuits and chips is preferred.
Experience with one or more formal verification platforms, such as Cadence Jasper, Synopsys VC Formal, or Siemens Questa Formal, is preferred.
Experience in formal verification applications such as data-path verification, sequential equivalence checking, and connectivity checking is preferred.
Experience formally proving the correctness of arithmetic units such as floating point adders and multipliers is preferred.
Experience working with schedulers, NOCs, networking topologies, and protocols such as AXI/AMBA is preferred.

Responsibilities

Define and drive the formal verification sign-off approach across complex IP and SoC designs using advanced formal techniques.
Architect, develop, and deploy reusable formal testbenches, methodology flows, and high-coverage SystemVerilog Assertions (SVA) suites across multiple designs and projects.
Collaborate with architecture and design teams to translate complex system and IP specifications into comprehensive formal verification test plans.
Maintain and enhance continuous integration, regression flows, and dashboarding to provide formal verification status and sign-off metrics.
Guide logic designers and verification engineers in incorporating formal methods into their workflows.
Contribute formal verification expertise to verify complex digital designs, focusing on TPU architecture and its integration within AI/ML-driven systems.
Contribute to ASICs used to accelerate computation in data centers, including project definition, formal verification, and silicon bring-up.
Participate in the architecture, documentation, and verification of the next generation of data center accelerators.

Define and drive the formal verification sign-off approach across complex IP and SoC designs, utilizing advanced formal techniques.
Architect, develop, and deploy reusable formal testbenches, methodology flows, and high-coverage SystemVerilog Assertions (SVA) suites across multiple designs and projects.
Collaborate with architecture and design teams to translate complex system and IP specifications into comprehensive formal verification test plans.
Maintain and enhance continuous integration, regression flows, and dashboarding to provide formal verification status and sign-off metrics.
Guide logic designers and verification engineers to effectively incorporate formal methods into their workflows.

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience in silicon development or ASIC/SoC design.
Experience with SystemVerilog Assertions (SVA) and formal verification methods.

Preferred qualifications:

Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture.
10 years of experience with industry standard tools, languages, and methodologies relevant to the development of silicon-based ICs and chips.
Experience with one or more formal verification platforms (e.g., Cadence Jasper, Synopsys VC Formal, or Siemens Questa Formal).
Experience in formal verification applications such as data-path verification, sequential equivalence checking, and connectivity checking.
Experience in formally proving correctness of arithmetic units such as floating point adders and multipliers.
Experience working with schedulers, NOCs and networking topologies, protocols (AXI/AMBA).

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As an ASIC Formal Verification Engineer, you'll contribute formal verification expertise to verify complex digital designs with a specific focus on TPU architecture and its integration within AI/ML-driven systems. You will be part of a team developing ASICs used to accelerate computation in data centers. You will have responsibilities in areas such as project definition, formal verification, and silicon bringup. You will participate in the architecture, documentation, and verification of the next generation of data center accelerators.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $237000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.In most instances, this position requires in-person interviews as part of the hiring process.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience in silicon development or ASIC/SoC design.
Experience with SystemVerilog Assertions (SVA) and formal verification methods.

About the Company

Google

Runs Search and YouTube and builds Gemini AI

Google runs the world's most used search engine and free services such as YouTube, Android, and Gmail, and it builds the Gemini AI models that work inside them. In 2017, its researchers invented the transformer, the neural network design behind ChatGPT and most other AI chatbots. People use these services without paying, and Google earns most of its money from ads placed beside search results and YouTube videos. Businesses rent computing power and Gemini models through Google Cloud, and Google also sells subscriptions and Pixel phones. Larry Page and Sergey Brin founded Google in 1998 as Stanford PhD students; it is based in Mountain View, California, United States, and is the main business of parent company Alphabet.

Company size: 10,001+
Company stage: IPO
Headquarters: Mountain View, CA
Founded: 1998

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