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Positron

Memory-first AI inference silicon for LLMs

Lead Emulation Test Engineer

Hardware Validation & TestingConfirmed live in the last 24 hours
Full-timeRemote

About the Job

Requirements

  • Extensive hands-on experience with Cadence Palladium Z1, Z2, or Z3, including advanced clocking, In-Circuit Emulation, and Virtual Interface flows.
  • A track record of emulating multi-billion-gate designs where partitioning, runtime predictability, and compile efficiency were critical.
  • Expert-level Python, Tcl, and Bash skills to build and maintain infrastructure for automated model releases and nightly regressions.
  • Proficiency in debugging low-level firmware and kernel-level issues using Verdi, SimVision, and hardware-software co-debug tools.
  • A BS or MS in Electrical Engineering, Computer Engineering, or Computer Science.
  • At least 8 years of experience in ASIC emulation or verification, with significant experience on large-scale Palladium installations.
  • Mastery of SystemVerilog, Verilog, and C/C++ for transactor development and reference modeling.
  • Deep understanding of data center protocols including PCIe, DDR, and AMBA AXI/NoC.

Responsibilities

  • Lead the partitioning and compilation of the design across a multi-rack Palladium environment, optimizing for performance and debug visibility.
  • Create and maintain hybrid emulation and co-simulation environments using SCE-MI or DPI, enabling software teams to boot operating system images and run AI workloads on pre-silicon hardware.
  • Design and execute comprehensive emulation test plans to verify high-speed interfaces including PCIe Gen 6/7, 112G+VSR, Ethernet, and complex AI memory hierarchies.
  • Use Palladium Dynamic Power Analysis and throughput monitors to identify peak performance and performance bottlenecks that simulation cannot capture.
  • Serve as the primary technical point of contact with Cadence R&D to troubleshoot tool issues and leverage Palladium Z3 capabilities.
  • Provide technical direction for pre-silicon validation of the next-generation AI inference ASIC.
  • Own the end-to-end emulation strategy on the Cadence Palladium platform, architecting complex model builds, managing multi-rack partitioning, and advancing software development earlier in the silicon cycle.
  • Collaborate with RTL, design verification, and software teams to build high-performance virtual environments that validate architectural functionality and accelerate firmware and operating-system bring-up before tape-out.
  • Set the emulation methodology, resolve hardware-software bottlenecks at scale, and ensure the design is silicon-ready.

About the Company

Positron

Memory-first AI inference silicon for LLMs

Positron develops memory-first AI inference silicon and systems to scale large-language-model serving. Its Atlas systems rely on commodity LPDDR5X memory rather than expensive HBM/CoWoS to boost bandwidth and capacity, enabling more efficient LLM deployment at hyperscale. The company’s next-generation Asimov silicon (tape-out planned for late 2026; production in 2027) pairs compute with very large memory per chip (roughly 288 GB to 2,304 GB) and is designed to be combined into Titan configurations (four to eight Asimov chips) for extremely large models and long context windows. Positron has already deployed Atlas systems in the cloud, including 50+ racks at Oracle Cloud Infrastructure and partnerships with Parasail, Jump Trading, and i3d.net. Its goal is to provide scalable, memory-rich AI inference hardware that lowers cost and increases throughput for serving large language models.

Company size
51-200
Company stage
Series C
Total funding
$1.2B
Headquarters
Reno, NV
Founded
2023

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