Quest Global

Engineering services, digital transformation, asset management

Verification Engineer

Hardware Validation & TestingConfirmed live in the last 24 hours

Full-timeBengaluru, Karnataka, IndiaNo salary listedIn-person

About the Job

Requirements

Strong hands-on experience in ASIC/SoC design verification.
Strong SystemVerilog knowledge.
Experience with UVM or an equivalent verification methodology.
Hands-on experience in one or more DFx/DFT areas, such as JTAG, scan/ATPG, MBIST/LBIST, IEEE 1500/1687, boundary scan, test compression, fuse/repair, or debug/trace.
Strong debugging and root-cause analysis skills.
Experience with simulation/debug tools such as VCS, Verdi, or equivalent.
Good understanding of RTL, clocks, resets, clock-domain crossing, and SoC architecture.
Strong scripting experience in Python, Perl, Tcl, Shell, or Ruby.
Experience with functional/code coverage and verification closure.
Bachelor’s or Master’s degree in Electrical, Electronics, or Computer Engineering, or a related field.

Responsibilities

Develop and execute DFx verification test plans based on architecture and design specifications.
Verify DFx features at IP, subsystem, and SoC levels.
Develop SystemVerilog/UVM testbenches, sequences, checkers, scoreboards, monitors, and coverage models.
Develop directed and constrained-random tests for DFx features.
Verify JTAG/IEEE 1149.x, IEEE 1500/1687, scan and ATPG, MBIST/LBIST, boundary scan, test compression, fuse/repair, clocks and resets, and on-chip debug/trace/observability features.
Execute simulation and regression environments and analyze failures to identify RTL, testbench, or design issues.
Perform root-cause analysis and work with RTL, DFT, architecture, and firmware teams to resolve issues.
Develop and maintain verification infrastructure, bus functional models, agents, and reusable verification components.
Analyze functional and code coverage, identify verification gaps, and drive coverage closure.
Support gate-level and scan-inserted simulations where required.
Work with emulation/FPGA platforms to extend DFx verification.
Collaborate with post-silicon and product engineering teams on silicon bring-up, pattern debug, and failure correlation.
Develop automation and regression scripts using Python, Perl, Tcl, Shell, or Make.
Participate in design and architecture reviews and provide DFx verification feedback.

Desired Qualifications

Experience with AMD, CPU, GPU, or server SoC architecture.
Experience with emulation or FPGA prototyping.
Knowledge of DFT/ATPG tools such as Tessent.
Experience with gate-level simulation and SDF.
Experience with silicon bring-up and post-silicon debug.
Knowledge of C/C++ and SystemVerilog DPI.
Exposure to formal verification, lint, and clock-domain-crossing methodologies.
Experience working with globally distributed engineering teams.

Job Requirements At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster. Role Summary We are looking for an experienced DV / DFx Verification Engineer to work on verification of Design-for-Test (DFT) and Design-for-Debug (DFD) features for complex AMD SoCs. The engineer will be responsible for developing verification plans, building SystemVerilog/UVM-based environments, creating tests, debugging regressions and driving coverage closure across IP, subsystem and SoC levels. Key Responsibilities Develop and execute DFx verification test plans based on architecture and design specifications. Verify DFx features at IP, subsystem and SoC levels. Develop SystemVerilog/UVM testbenches, sequences, checkers, scoreboards, monitors and coverage models. Develop directed and constrained-random tests for DFx features. Verify DFT/DFx features including: JTAG / IEEE 1149.x IEEE 1500 / 1687 Scan and ATPG MBIST / LBIST Boundary Scan Test compression Fuse / repair Clocks and resets On-chip debug / trace / observability Execute simulation and regression environments and analyze failures to identify RTL, testbench or design issues. Perform root-cause analysis and work closely with RTL, DFT, architecture and firmware teams to resolve issues. Develop and maintain verification infrastructure, BFMs, agents and reusable verification components. Analyze functional and code coverage, identify verification gaps and drive coverage closure. Support gate-level and scan-inserted simulations where required. Work with emulation/FPGA platforms to extend DFx verification. Collaborate with post-silicon and product engineering teams for silicon bring-up, pattern debug and failure correlation. Develop automation and regression scripts using Python / Perl / Tcl / Shell / Make. Participate in design and architecture reviews and provide DFx verification feedback. Mandatory Skills Strong hands-on experience in ASIC/SoC Design Verification. Strong SystemVerilog knowledge. Experience with UVM or equivalent verification methodology. Hands-on experience with one or more DFx/DFT areas such as: JTAG Scan / ATPG MBIST / LBIST IEEE 1500 / 1687 Boundary Scan Test compression Fuse / repair Debug / trace Strong debugging and root-cause analysis skills. Experience with simulation/debug tools such as VCS, Verdi or equivalent. Good understanding of RTL, clocks, resets, CDC and SoC architecture. Strong scripting experience in Python, Perl, Tcl, Shell or Ruby. Experience with functional/code coverage and verification closure. Good to Have Experience with AMD/CPU/GPU/Server SoC architecture. Experience with emulation or FPGA prototyping. Knowledge of DFT/ATPG tools such as Tessent. Experience with gate-level simulation and SDF. Experience with silicon bring-up and post-silicon debug. Knowledge of C/C++ and SystemVerilog DPI. Exposure to formal verification, lint and CDC methodologies. Experience working with globally distributed engineering teams. Education Bachelor’s or Master’s degree in Electrical / Electronics / Computer Engineering or a related field. We are known for our extraordinary people who make the impossible possible every day. Questians are driven by hunger, humility, and aspiration. We believe that our company culture is the key to our ability to make a true difference in every industry we reach. Our teams regularly invest time and dedicated effort into internal culture work, ensuring that all voices are heard. We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace.

About the Company

Quest Global

Engineering services, digital transformation, asset management

QuEST Global provides engineering and lifecycle services across aerospace, automotive, energy, healthcare, and transportation, focusing on digital transformation and asset management. It uses edge computing, cloud, AI/ML, and industrial IoT to deliver tailored engineering solutions through long-term partnerships, service contracts, project-based engagements, and strategic collaborations. It differentiates itself with a broad industry footprint, global delivery model, and emphasis on partnerships, talent development, and workplace culture. Its goal is to help clients improve operational efficiency and drive business growth by transforming engineering processes and assets with digital tools and data-driven management.

Company size: 10,001+
Company stage: Growth Equity (Venture Capital)
Total funding: $581M
Headquarters: Greenville, SC
Founded: 1997

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